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| Number | Title | Issue Date |
| 8135941 | Vector morphing mechanism for multiple processor cores One embodiment of the invention provides a processor. The processor generally includes a first and second processor core, each having a plurality of pipelined execution units for executing an issue group of multiple instructions and scheduling logic configured to is... | 03/13/2012 |
| 8074055 | Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code A computer. A processor pipeline alternately executes instructions coded for first and second different computer architectures or coded to implement first and second different processing conventions. A memory stores instructions for execution by the processor pipeli... | 12/06/2011 |
| 7856546 | Configurable processor module accelerator using a programmable logic device A configurable processor module accelerator using a programmable logic device is described. According to one embodiment, the accelerator module includes a circuit board having coupled thereto a first programmable logic device, a controller, and a first memory. The f... | 12/21/2010 |
| 7725682 | Method and apparatus for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit Methods and apparatus are provided for sharing storage and execution resources between architectural units in a microprocessor using a polymorphic function unit. A method for executing instructions in a processor having a polymorphic execution unit includes the step... | 05/25/2010 |
| 7676649 | Computing machine with redundancy and related systems and methods According to an embodiment of the invention, a computing machine comprises a pipeline accelerator, a host processor coupled to the pipeline accelerator, and a redundant processor, a redundant pipeline unit, or both, coupled to the host processor and to the pipeline ... | 03/09/2010 |
| 7627739 | Optimization of a hardware resource shared by a multiprocessor Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource... | 12/01/2009 |
| 7577823 | Wake-up and sleep conditions of processors in a multi-processor system The present invention relates to a multi-processor computer system comprising at least two processors for parallel execution of processes, at least two cache memory units, each being associated with and connected t... | 08/18/2009 |
| 7526632 | System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing A system, apparatus and a method for implementing multifunctional memories is disclosed. The multifunctional memories perform a variety of functions during execution of extended instructions in a reconfigurable data path processor composed of processing nodes. In on... | 04/28/2009 |
| 7509480 | Selection of ISA decoding mode for plural instruction sets based upon instruction address An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to different ISAs during execution of a multiple-ISA application program.... | 03/24/2009 |
| 7493472 | Meta-address architecture for parallel, dynamically reconfigurable computing A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Eac... | 02/17/2009 |
| 7487330 | Method and apparatus for transferring control in a computer system with dynamic compilation capability In a dynamically compiling computer system, a system and method for efficiently transferring control from execution of an instruction in a first representation to a second representation of the instruction is disclosed. The system and method include the setting of a... | 02/03/2009 |
| 7437532 | Memory mapped register file A memory mapped register file is disclosed for a data processing system that comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of registers addressable by an encoded address, wherein the encoded address corresponds to a res... | 10/14/2008 |
| 7430678 | Low power operation control unit and program optimizing method An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performin... | 09/30/2008 |
| 7424595 | System for managing circuitry of variable function information processing circuit and method for managing circuitry of variable function information processing circuit Configuration management information having circuit configuration information for altering a circuit configuration of an FPGA (12) is stored in a memory (13), the configuration management information according to information related to an instruction g... | 09/09/2008 |
| 7421571 | Apparatus and method for switching threads in multi-threading processors A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the first instruction fetch unit and the second instruction fetch unit. An ... | 09/02/2008 |
| 7398410 | Processor employing a power managing mechanism and method of saving power for the same A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power controller configured to control the status of the execution unit based on ... | 07/08/2008 |
| 7395416 | Computer processing system employing an instruction reorder buffer A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of processors to execute the dependence chains on execution pipelines; implement... | 07/01/2008 |
| 7389405 | Digital signal processor architecture with optimized memory access for code discontinuity A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code discontinuity is encountered, the unified memory is accessed a first time ... | 06/17/2008 |
| 7373440 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to s... | 05/13/2008 |
| 7366891 | Methods and apparatus to provide dual-mode drivers in processor systems Methods and apparatus to provide dual-mode drivers in a processor system are disclosed. An example method disclosed herein comprises including operating system (OS) agnostic mode services that are available during an OS agnostic mode to allow a single set of drivers... | 04/29/2008 |
| 7363625 | Method for changing a thread priority in a simultaneous multithread processor An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority... | 04/22/2008 |
| 7360005 | Software programmable multiple function integrated circuit module An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable func... | 04/15/2008 |
| 7356673 | System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second instruction set in a plurality of buffers proximate to a plurality of exe... | 04/08/2008 |
| 7356670 | Data processing system A multiprocessor data processing system is described wherein the processors communicate to each other via a shared memory. Each of the processors comprises an administration unit (18a) and a computational unit. The administration unit of a writing proc... | 04/08/2008 |
| 7353446 | Cyclic redundancy check circuit for use with self-synchronous scramblers The present invention provides a circuit for detecting and correcting errors in a bit stream. At least two logic gates receive inputs from a plurality of circuit elements. The plurality of circuit elements are coupled to receive and store a portion of a bit stream. ... | 04/01/2008 |
| 7353362 | Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means con... | 04/01/2008 |
| 7353368 | Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, p... | 04/01/2008 |
| 7340625 | Process and apparatus for reducing power usage microprocessor devices operating from stored energy sources A process and apparatus for preparing said process for reducing the power consumption of microprocessor-based devices by reducing the frequency of the oscillator governing the logical operation of the microprocessor during periods of use in which system performance ... | 03/04/2008 |
| 7333520 | Apparatus for multiplexing signals through I/O pins One embodiment of the present invention provides an apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip. This apparatus includes an I/O pin, for coupling a signal line within the semiconductor chip to a signa... | 02/19/2008 |
| 7325221 | Logic system with configurable interface A core block with a highly configurable interface such that the interface of the core can be optimally configured for the system the core is integrated into. In one embodiment the method consists of defining a configurable interface with different configuration opti... | 01/29/2008 |
| 7318141 | Methods and systems to control virtual machines Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS compon... | 01/08/2008 |
| 7313643 | PCI-express to PCI/PCI X translator An apparatus for converting a PCI/PCI X device into a PCI-Express device. The apparatus may include a first circuit configured to receive first data, wherein the first circuit is configured to translate the first data into PCI formatted data. The apparatus may also ... | 12/25/2007 |
| 7295334 | Image processing apparatus having configurable processors An image processing apparatus includes at least two signal processor modules interconnected each other in series. Each of the signal processor modules has an input port through which data is input, a memory which stores data, a signal processor portion which carries... | 11/13/2007 |
| 7290089 | Executing cache instructions in an increased latency mode For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle a... | 10/30/2007 |
| 7263602 | Programmable pipeline fabric utilizing partially global configuration buses A method of associating virtual stripes to physical stripes in a pipelined or ring structure comprises associating a first set of virtual stripes with at least two physical stripes and associating a second set of virtual stripes, disjoint from the first set, with at... | 08/28/2007 |
| 7254691 | Queuing and aligning data Queuing and ordering data is described. Data is stored or queued in concatenated memories where each of the memories has a respective set of data out ports. An aligner having multiplexers arranged in a lane sequence are coupled to each set of the data out ports. A v... | 08/07/2007 |
| 7251594 | Execution time modification of instruction emulation parameters To improve computer performance, problems of emulation such as WAR hazard, uneven utilization of machine resources, unnecessary dependencies, wasted hardware resources and data buffer pollution, are alleviated by responding to dynamic execution information, such as ... | 07/31/2007 |
| 7237099 | Multiprocessor system having a plurality of control programs stored in a continuous range of addresses of a common memory and having identification registers each corresponding to a processor and containing data used in deriving a starting address of a CPU-linked interrupt handler program to be executed by the corresponding processor A multiprocessor system has a plurality of CPUs with respective local buses, and a memory which stores a plurality of programs to be executed by the CPUs and is connected to a common bus which can be accessed via the local buses, each local bus being connected to a ... | 06/26/2007 |
| 7237216 | Clock gating approach to accommodate infrequent additional processing latencies A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal... | 06/26/2007 |
| 7231630 | Method and system automatic control of graphical computer application appearance and execution A method and system are provided for controlling a computer, data, or media system in response to state changes in the computer system. At least one state table having a first dimension and a second dimension is created. At least one programming element is listed al... | 06/12/2007 |
