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The Quarterly Review ; March edition, 1825
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| Number | Title | Issue Date |
| 8108652 | Vector processing with high execution throughput The claimed invention is an efficient and high-performance vector processor. Through minimizing the use of multiple banks of memory and/or multi-ported memory blocks to reduce implementation cost, vector memory 450 provides abundant memory bandwidth and enabl... | 01/31/2012 |
| 7793072 | Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands A microprocessor including an execution unit enabled to execute an asymmetric instruction, where the asymmetric instruction includes a set of operand fields and an operation code (opcode). The execution unit is configured to interpret the opcode to perform a first o... | 09/07/2010 |
| 7793073 | Method and apparatus for indirectly addressed vector load-add-store across multi-processors A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 09/07/2010 |
| 7725678 | Method and apparatus for producing an index vector for use in performing a vector permute operation A method for generating a permutation index vector includes receiving a condition vector and performing an index generation function using the condition vector in order to generate the permutation index vector. An index vector generation circuit is also disclosed. | 05/25/2010 |
| 7516299 | Splat copying GPR data to vector register elements by executing lvsr or lvsl and vector subtract instructions A method for transferring data from a general purpose register (GPR) to a vector register (VR), the method including vectorially combining data in the VR from the GPR, by executing instructions of a PowerPC Instruction Set Architecture (ISA), the step of combining i... | 04/07/2009 |
| 7496731 | Two dimensional addressing of a matrix-vector register array A method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has ... | 02/24/2009 |
| 7467287 | Method and apparatus for vector table look-up Methods and apparatuses for performing vector table look-up using multiple look-up tables. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a plurality of numbers; partitioni... | 12/16/2008 |
| 7421565 | Method and apparatus for indirectly addressed vector load-add -store across multi-processors A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 09/02/2008 |
| 7404065 | Flow optimization and prediction for VSSE memory operations In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instructio... | 07/22/2008 |
| 7386703 | Two dimensional addressing of a matrix-vector register array A processor and method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Ea... | 06/10/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7366873 | Indirectly addressed vector load-operate-store method and apparatus A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 04/29/2008 |
| 7363478 | Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruc... | 04/22/2008 |
| 7356568 | Method, processing unit and data processing system for microprocessor communication in a multi-processor system A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Eac... | 04/08/2008 |
| 7353371 | Circuit to extract nonadjacent bits from data packets A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination data fields in a result packet governed by a field locator packet. I... | 04/01/2008 |
| 7353503 | Efficient dead code elimination Disclosed is a method for eliminating dead code from a computer program using an operands graph generated from a flow graph of a computer program. In one embodiment of the present invention, the operands graph is traversed for any unused operands. Upon detection of ... | 04/01/2008 |
| 7350057 | Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an ins... | 03/25/2008 |
| 7343572 | Vector interface to shared memory in simulating a circuit design A first block, a second block, a shared memory, and a third block are generated in a circuit design in response to user input control. The first block is coupled to the second block, the second block is coupled to the shared memory, and the shared memory is coupled ... | 03/11/2008 |
| 7343542 | Methods and apparatuses for variable length encoding Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality o... | 03/11/2008 |
| 7315932 | Data processing system having instruction specifiers for SIMD register operands and method thereof Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 01/01/2008 |
| 7313788 | Vectorization in a SIMdD DSP architecture A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access pattern of data required for implementing the loop in the architecture... | 12/25/2007 |
| 7302627 | Apparatus for efficient LFSR calculation in a SIMD processor The apparatus provides for efficient implementation of multiple-bit leap-forward LFSRu calculation in a SIMD processor. This provides an accelerated and programmable way to implement LFSR calculations in a SAID processor. Conditional vector exclusive-OR accumulation... | 11/27/2007 |
| 7296258 | Software management systems and methods for automotive computing devices Methods and systems for operating automotive computing devices are described. In one embodiment, a small amount of static RAM (SRAM) is incorporated into an automotive computing device. The SRAM is battery-backed to provide a non-volatile memory space in which criti... | 11/13/2007 |
| 7293258 | Data processor and method for using a data processor with debug circuit A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of multi-bit subfields of a vector operand independently. Debug action ... | 11/06/2007 |
| 7275246 | Executing programs for a first computer architecture on a computer of a second architecture Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context... | 09/25/2007 |
| 7275148 | Data processing system using multiple addressing modes for SIMD operations and method thereof Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 09/25/2007 |
| 7269595 | Reducing database reorganization time The invention provides a system and method for reducing the amount of downtime during a database reorganization. The invention provides a method whereby data values are unloaded from a table in a database, stored in a substantially original format in another locatio... | 09/11/2007 |
| 7266824 | Address space priority arbitration A digital system and method of operation is provided in which several processors (400[]) are connected to a shared resource (432). Each processor has a translation lookaside buffer (TLB) (310[]) that contains recently used page entries that each... | 09/04/2007 |
| 7262722 | Hardware-based CABAC decoder with parallel binary arithmetic decoding A binary arithmetic decoding apparatus includes first, second and third pairs of look-up tables and first, second and third multiplexers. The first multiplexer selects between the respective outputs of the two look-up tables of the first pair of look-up tables. The ... | 08/28/2007 |
| 7257695 | Register file regions for a processing system According to some embodiments, a dynamic region in a register file may be described for an operand. The described region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information ... | 08/14/2007 |
| 7254696 | Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit th... | 08/07/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7240285 | Encoding and distribution of schema for multimedia content descriptions The encoding and distribution of schema for multimedia content descriptions are described. Before the schema is sent to a system for use, it is encoded by assigning a first token for each component in the schema and a second token for each attribute of each componen... | 07/03/2007 |
| 7230633 | Method and apparatus for image blending Methods and apparatuses for blending two images using vector table look up operations. In one aspect of the invention, a method to blend two images includes: loading a vector of keys into a vector register; converting the vector of keys into a first vector of blendi... | 06/12/2007 |
| 7228404 | Managing instruction side-effects A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the represe... | 06/05/2007 |
| 7219212 | Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maint... | 05/15/2007 |
| 7219336 | Tracking format of registers having multiple content formats in binary translation In one embodiment of the invention, a register format of a source register operated on by a source instruction in a source block of code is determined. The register format includes an input instruction format and an output block format of the source block of code. T... | 05/15/2007 |
| 7216218 | Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a comput... | 05/08/2007 |
| 7210023 | Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements, and a processor operable to... | 04/24/2007 |
| 7210126 | Using identifiers and counters for controlled optimization compilation The invention enables a compiler (during its first compilation pass) to insert identifiers during an early optimization phase into machine-independent code. The identifiers are used for identifying specific instructions of the machine-independent code. The compiler ... | 04/24/2007 |
