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| Number | Title | Issue Date |
| 8090929 | Generating clock signals for coupled ASIC chips in processor interface with X and Y logic operable in functional and scanning modes A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first proce... | 01/03/2012 |
| 7822946 | On-chip packet interface processor encapsulating memory access from main processor to external system memory in serial packet switched protocol A computing and communication chip architecture is provided wherein the interfaces of processor access to the memory chips are implemented as a high-speed packet switched serial interface as part of each chip. In one embodiment, the interface is accomplished through... | 10/26/2010 |
| 7660968 | Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow th... | 02/09/2010 |
| 7587579 | Processor core interface for providing external hardware modules with access to registers of the core and methods thereof A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core.... | 09/08/2009 |
| 7409531 | Integrated micro-controller and programmable device A single-IC subsystem controller for controlling electronic devices and subsystems within computer systems and other large electronic systems. The single-IC subsystem controller includes a micro-controller, a complex programmable logic device, an EEPROM, an SRAM, an... | 08/05/2008 |
| 7363441 | Portable storage apparatus and method for freely changing data bus width A portable storage apparatus capable of freely changing a data bus width and a method of setting the data bus width of the apparatus are provided, where the portable storage apparatus has at least one command line and a plurality of data lines and includes a non-vol... | 04/22/2008 |
| 7327159 | Interface block architectures In accordance with an embodiment of the present invention, a programmable logic device includes a memory adapted to store information in the programmable logic device, an input/output circuit adapted to transfer information into or out of the programmable logic devi... | 02/05/2008 |
| 7315388 | Image input/output control apparatus, image processing apparatus, image processing method, data communication apparatus, and data communication method An image input/output control apparatus includes a control device for controlling input/output of image data with an external apparatus, plural image processing devices for performing predetermined image processes to the image data, and plural data transfer devices ... | 01/01/2008 |
| 7305540 | Method and apparatus for data processing Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling the host memory comprising DRAM memory, the memory controller coupled ... | 12/04/2007 |
| 7305543 | Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, e... | 12/04/2007 |
| 7290124 | Data processor employing register banks with overflow protection to enhance interrupt processing and task switching The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception o... | 10/30/2007 |
| 7287147 | Configurable co-processor interface A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The coprocessor interface has an instruction transfer signal group for transferring different instruction types from the CPU to the coprocessor, sequentially ... | 10/23/2007 |
| 7287148 | Unified shared pipeline allowing deactivation of RISC/DSP units for power saving An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and t... | 10/23/2007 |
| 7287153 | Processing of processor performance state information A basic input/output system (BIOS) evaluates a plurality of performance state data that is stored in a disposable memory to determine if one of the plurality matches a set of processor criteria, which correspond to a processor of the computer system. Each of the plu... | 10/23/2007 |
| 7275103 | Storage path optimization for SANs Embodiments of a system and method for rule-based proactive storage path optimization for SANs. Embodiments may evaluate paths between an application and its storage on a SAN based on current and/or historical path quality of service. Performance of alternative path... | 09/25/2007 |
| 7263627 | System and method having strapping with override functions A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be te... | 08/28/2007 |
| 7251485 | Wireless LAN terminal device, portable data terminal system, mobile phone, wireless LAN communication method, method for providing service, and method for transferring incoming call A portable wireless LAN terminal device attachable to an external connecting terminal installed in a portable external connection device, such as a portable data terminal device, includes a device body (2); means for transmitting and receiving (6-9 | 07/31/2007 |
| 7248838 | Wireless communication system within a system on a chip A communication system for transmitting data between cores embedded in an integrated circuit on a silicon chip. Communication system includes transmitter circuitry for wirelessly transmitting data between cores and receiver circuitry for wirelessly receiving the tra... | 07/24/2007 |
| 7240157 | System for handling memory requests and method thereof A system and methods are shown for handling multiple target memory requests. Memory read requests generated by a peripheral component interconnect (PCI) client are received by a PCI bus controller. The PCI bus controller passes the memory request to a memory control... | 07/03/2007 |
| 7237092 | Microprocessor circuit for portable data carriers and method for operating the circuit A microprocessor circuit includes a control unit, a memory for free programming with at least one program having functions, a stack for buffer-storing data, a register bank having at least one register, and an auxiliary register that stores a number of bits, each of... | 06/26/2007 |
| 7234031 | Portable storage apparatus and method for freely changing data bus width A portable storage apparatus capable of freely changing a data bus width and a method of setting the data bus width of the apparatus are provided, where the portable storage apparatus has at least one command line and a plurality of data lines, and includes a non-vo... | 06/19/2007 |
| 7233166 | Bus state keepers Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in r... | 06/19/2007 |
| 7231552 | Method and apparatus for independent control of devices under test connected in parallel A JTAG-compatible device includes a unique identifier stored in dedicated non-volatile memory, a test access port (TAP) controller, a TAP instruction register, a dedicated data register, and a comparison block. The TAP instruction register enables and/or disables TA... | 06/12/2007 |
| 7230953 | Method and system for controlling UTOPIA buses According to one embodiment of the invention, a system for managing communication in a network line card is provided. The system includes at least two UTOPIA bus controllers. Each UTOPIA bus controller is operable to control a particular one of a plurality of UTOPIA... | 06/12/2007 |
| 7230445 | System monitor in a programmable logic device Method and apparatus for a system monitor embedded in a programmable logic device are described. The system monitor includes a dynamic reconfiguration port interface for configuring or reconfiguring the system monitor during operation thereof. The system monitor inc... | 06/12/2007 |
| 7228401 | Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor The present invention relates generally to interfacing a processor with at least one coprocessor. One embodiment relates to a processor having a set of broadcast specifiers which it uses to selectively broadcast an operand that is being written to a register within ... | 06/05/2007 |
| 7225383 | System and method for enhancing communication between devices in a computer system An apparatus and method for resending a request in a computer system using a delay value is provided. In response to receiving a request, a target device in a computer system may detect that it is temporarily unable to process the request. The target device can send... | 05/29/2007 |
| 7221203 | Pulse-width modulator circuit and method for controlling a pulse width modulator circuit The invention relates to a pulse width modulator circuit for generating a reference signal having a desired duty cycle comprising an adjustment unit including at least one storage register and a counter, the storage register being configured for storing values corre... | 05/22/2007 |
| 7213128 | Storing and transferring SIMD saturation history flags and data size A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A coprocessor instruction has a format identifying a saturating operation, a first source having packed da... | 05/01/2007 |
| 7209995 | Efficient connection between modules of removable electronic circuit cards A removable electronic circuit card has multiple modules connected to the card's bus in parallel so that each module can exchange commands and data independently with the host. According to a first aspect of the present invention, this achieved by a controller-to-co... | 04/24/2007 |
| 7194600 | Method and apparatus for processing data with a programmable gate array using fixed and programmable processors A method and apparatus for processing data within a programmable gate array comprise a first fixed logic processor and a second fixed logic processor that are embedded within the programmable gate array and detect a custom operation code. The processing continues wh... | 03/20/2007 |
| 7191318 | Native copy instruction for file-access processor with copy-rule-based validation A copy instruction executed by a functional-level instruction-set computing (FLIC) processor copies a variable-length data block from one resource to another resource through a cross-bar switch. Resources include general-purpose registers, input, output, and executi... | 03/13/2007 |
| 7180519 | Image processing apparatus and image process method In a pipeline process in which plural image processing sections (image processing modules), for example, an image inputting section 131, a histogram producing section 132, and a binarizing section 133 are connected in a pipeline manner, each of ... | 02/20/2007 |
| 7171542 | Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable inter... | 01/30/2007 |
| 7165199 | Tap time division multiplexing An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test data, wherein the test data is clocked in a plurality of time slots, with test data for different o... | 01/16/2007 |
| 7162563 | Semiconductor integrated circuit having changeable bus width of external data signal A data controlling unit activates a predetermined number of data terminals according to a mode signal and changes a bus width of external data signal. According to the mode signal, an address controlling unit selects a predetermined number of bits of an internal add... | 01/09/2007 |
| 7155550 | Program-executing apparatus and portable information processing apparatus A program-executing apparatus has a simple configuration, is capable of executing high-speed processing, and is capable of providing high security. The apparatus is configured such that a host system wherein a program execution environment using a general-purpose OS... | 12/26/2006 |
| 7134118 | Re-programmable flash memory micro controller as programmable logic controller Functions of a programmable logic controller are located in physically separable units. These physically separable units include a program execution device, or control device, whose function is limited to sequencing through the user logic program and a communication... | 11/07/2006 |
| 7130963 | System and method for instruction memory storage and processing based on backwards branch control information A system for instruction memory storage and processing in a computing device having a processor, the system is based on backwards branch control information and comprises a dynamic loop buffer (DLB) which is a tagless array of data organized as a direct-mapped struc... | 10/31/2006 |
| 7126375 | Floor plan for scalable multiple level tab oriented interconnect architecture A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the ... | 10/24/2006 |
