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| Number | Title | Issue Date |
| 7975126 | Reconfiguration of execution path upon verification of extension security information and disabling upon configuration change in instruction extensible microprocessor Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle... | 07/05/2011 |
| 7937559 | System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes A processor generation system includes the ability to describe processors with three instruction sizes. In one example implementation, instructions can be 16-, 24- and 64-bits. This enables a new range of architectures that can exploit parallelism in architectures. ... | 05/03/2011 |
| 7886130 | Field programmable gate array and microcontroller system-on-a-chip A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherei... | 02/08/2011 |
| 7653805 | Processing in pipelined computing units with data line and circuit configuration rule signal line A semiconductor device for performing data processing by performing a plurality of computations in cycles includes a pipeline formed by connecting a plurality of computing units in series, each of the computing units including: a data line for receiving data; a cont... | 01/26/2010 |
| 7653806 | Method and apparatus for performing improved group floating-point operations Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data ... | 01/26/2010 |
| 7613901 | Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associate... | 11/03/2009 |
| 7587578 | Processing only those that need processing among divided portions of input data and binding with unprocessed portions while allowing reconfiguration of processing logic device for next input Provided is a reconfigurable processor or apparatus capable of changing a logic without any loss of input data and without any deterioration of data computing processing performance, which is impossible with a conventional reconfigurable processor or apparatus. The ... | 09/08/2009 |
| 7568085 | Scalable FPGA fabric architecture with protocol converting bus interface and reconfigurable communication path to SIMD processing elements A field programmable gate array includes a virtual bus interface that receives a control word from a host processor over a standard I/O bus. A configurable very long instruction word (VLIW) controller receives the control word via virtual bus interface signals mappe... | 07/28/2009 |
| 7539848 | Configurable logic fabric including two fixed logic processors with individual interface to receive availability signal from custom operation code configured processor A system is disclosed comprising a logic circuit in an integrated circuit device, wherein the logic circuit comprises a logic fabric that includes a plurality of configurable logic blocks, switching blocks, and input/output blocks, wherein the logic fabric is config... | 05/26/2009 |
| 7529910 | Series and parallel operation of reconfigurable circuits with selection and timing buffers assembly for processing and binding divided data portions in matched timing A reconfigurable processor equipped with reconfigurable circuits (RCs) comprises unit A for dividing data input to the processor, and outputting a part of pieces of divided data to a RC, unit B for selecting or binding at least one piece of divided data among divide... | 05/05/2009 |
| 7529909 | Security verified reconfiguration of execution datapath in extensible microcomputer Described is microprocessor architecture that includes at least one reconfigurable execution path (e.g., implemented via FPGAs or CPLDs). When an instruction is fetched, a mechanism determines whether the reconfigurable execution path (and/or which path) will handle... | 05/05/2009 |
| 7409531 | Integrated micro-controller and programmable device A single-IC subsystem controller for controlling electronic devices and subsystems within computer systems and other large electronic systems. The single-IC subsystem controller includes a micro-controller, a complex programmable logic device, an EEPROM, an SRAM, an... | 08/05/2008 |
| 7373432 | Programmable circuit and related computing machine and method A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a system, such as a computing machine, to modify the programmable circuit... | 05/13/2008 |
| 7368940 | Programmable integrated circuit with selective programming to compensate for process variations and/or mask revisions Programmable integrated circuits (ICs) that compensate for process variations and/or mask revisions in a programmable integrated circuit (IC). An exemplary IC includes two programming ports, two programmable circuits (e.g., digital and analog), a non-volatile memory... | 05/06/2008 |
| 7363237 | Enforcement process for correction of hardware and software defects A method and apparatus for improvement of computer-related products to solve problems caused by artificially embedded locks, barriers, defects, and the like, that force a consumer to needlessly upgrade hardware or software on a computer. An independent developer may... | 04/22/2008 |
| 7356672 | Warp processor for dynamic hardware/software partitioning A warp processor includes a microprocessor, profiler, dynamic partitioning module, and warp configurable logic architecture. The warp processor initially executes a binary for an application entirely on the microprocessor, the profiler monitors the execution of the ... | 04/08/2008 |
| 7350013 | Bus communication apparatus for programmable logic devices and associated methods A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry ... | 03/25/2008 |
| 7343594 | Software-to-hardware compiler with symbol set inference analysis A software-to-hardware compiler is provided that generates hardware constructs in programmable logic resources. The programmable logic resources may be optimized in terms of being configured to make additional copies of regions on memory devices other than on the pr... | 03/11/2008 |
| 7337301 | Designing configurable processor with hardware extension for instruction extension to replace searched slow block of instructions A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing har... | 02/26/2008 |
| 7330979 | Method for protecting the processing of sensitive information in a monolithic security module, and associate security module The invention relates to a method and associated security module for protecting the processing of sensitive information in a security module with a monolithic structure, the module comprising information processing means (9) and means for storing (3, 4... | 02/12/2008 |
| 7325123 | Hierarchical interconnect for configuring separate interconnects for each group of fixed and diverse computational elements An integrated circuit having computational elements. As least one of the computational elements has a fixed architecture. An interconnection network is coupled to a first group of the computational elements to configure the first group for a first operation. An inte... | 01/29/2008 |
| 7324401 | Memory device and method having programmable address configurations A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, addr... | 01/29/2008 |
| 7318141 | Methods and systems to control virtual machines Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS compon... | 01/08/2008 |
| 7317958 | Apparatus and method of additive synthesis of digital audio signals using a recursive digital oscillator A method of performing additive synthesis of digital audio signals using a novel recursive digital oscillator includes the step of receiving digital audio signal frames wherein each digital audio signal frame includes a set of frequency, amplitude, and phase compone... | 01/08/2008 |
| 7299342 | Complex vector executing clustered SIMD micro-architecture DSP with accelerator coupled complex ALU paths each further including short multiplier/accumulator using two's complement A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions.... | 11/20/2007 |
| 7287189 | I/O configuration and reconfiguration trigger through testing interface A reconfigurable device loads I/O configuration information from a diagnostic interface during testing. The device includes a configurable I/O connection for communicating values with other devices. A diagnostic interface communicates the value of the I/O connection... | 10/23/2007 |
| 7277039 | Semiconductor integrated circuit with A/D converter having a ladder-type resistor A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first op... | 10/02/2007 |
| 7274212 | Methods and apparatus for control and configuration of programmable logic device Circuitry and methods are provided for control and configuration of a PLD. An embodiment of the invention comprises hard IP circuitry embedded in the PLD. The circuitry may include a gigabit MAC, a hard processor, and a DMA engine. The invention permits a variety of... | 09/25/2007 |
| 7260631 | System and method for receiving iSCSI protocol data units An Internet small computer system interface (iSCSI) system, method and associated data structure are provided for receiving data in protocol data units. After a protocol data unit is received, a data list is identified that describes how the data contained in the pr... | 08/21/2007 |
| 7257780 | Software-to-hardware compiler A hardware-to-software compiler is provided that runs an optimization on a circuit implemented in programmable logic. The optimization allows portions of the program implemented by the circuit to be executed via software. A communication interface between the hardwa... | 08/14/2007 |
| 7257654 | PCI bridge device configured for using JTAG scan for writing internal control registers and outputting debug state An integrated device (e.g., an integrated PCI bridge device), having configuration registers for storing configuration values, device logic for generating internal state values based on the configuration values, and a JTAG interface configured for receiving a serial... | 08/14/2007 |
| 7257715 | Semiconductor integrated circuit A semiconductor integrated circuit including one or a plurality of external functional blocks; a nonvolatile memory having a logical content as to whether to validate or invalidate the external functional blocks; and a logical circuit validating or invalidating an i... | 08/14/2007 |
| 7254800 | Methods of providing error correction in configuration bitstreams for programmable logic devices Methods of providing error correction in configuration bitstreams for programmable logic devices (PLDs). While any error correction method can be used, in one embodiment a Hamming code is applied to instructions in the configuration bitstream, while a product code i... | 08/07/2007 |
| 7248757 | Method, device and computer program for designing a circuit having electric wires and optical connections A design method and a design device can design an optimal optoelectronic circuit in a relatively short period of time by exploiting the performance of hardware. They have a step of generating a connection list to be carried by electric circuits (electric nets) and a... | 07/24/2007 |
| 7249279 | Multiprocessor code fix using a local cache Operating code fixes are supplied to multiple processors utilizing the same operating code by storing the correction code fixes in a central RAM, and distributing the code fixes over a dedicated code fix bus to a local cache for each processor. The first processor e... | 07/24/2007 |
| 7249306 | System and method for generating 128-bit cyclic redundancy check values with 32-bit granularity A System and Method for generating Cyclic Redundancy Check (CRC) values in a system adapted simultaneously handling a plurality of blocks in parallel is described. Included is a memory or other storage device for storing data blocks, wherein the memory or storage de... | 07/24/2007 |
| 7242218 | Techniques for combining volatile and non-volatile programmable logic on an integrated circuit Techniques for combining volatile and non-volatile programmable logic into one integrated circuit (IC) are provided. An IC is segregated into two portions. A first block of programmable logic is configured by bits stored in on-chip non-volatile memory. A second bloc... | 07/10/2007 |
| 7243206 | Method and apparatus for using a RAM memory block to remap ROM access requests A method and data processing apparatus for remapping selected data access requests issued by a processor for accessing data items stored on a ROM. The method comprises the following steps: storing at least one replacement data item corresponding to at least one data... | 07/10/2007 |
| 7237055 | System, apparatus and method for data path routing configurable to perform dynamic bit permutations A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In... | 06/26/2007 |
| 7236525 | Reconfigurable computing based multi-standard video codec A circuit generally comprising a multiport memory, a direct memory access engine and a programmable gate array is disclosed. The direct memory access engine may be configured to transfer a first program to the multiport memory. The programmable gate array may be con... | 06/26/2007 |
