Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 7900022 | Programmable processing unit with an input buffer and output buffer configured to exclusively exchange data with either a shared memory logic or a multiplier based upon a mode instruction In general, in one aspect, a processing unit includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control stor... | 03/01/2011 |
| 7809927 | Computation parallelization in software reconfigurable all digital phase lock loop A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any othe... | 10/05/2010 |
| 7707386 | Program segment searching for extension instruction determination to design a processor that meets performance goal A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing ... | 04/27/2010 |
| 7694108 | Reconfigurable semiconductor device capable of controlling output timing of data An arithmetic unit capable of reconfiguring circuitry in accordance with configuration data supplied includes a data processing unit performing a processing using input data; an output data maintenance unit maintaining the result of the processing to output it as an... | 04/06/2010 |
| 7536533 | MCU based motor controller with pre-load register and DMA controller A method is disclosed for generating a sequential pattern of motor control instructions under control of a microcontroller for the purpose of controlling a motor. A pattern of motor control instructions is stored in a memory. A timing circuit is operable to generate... | 05/19/2009 |
| 7529908 | Method and apparatus for unified exception handling with distributed exception identification A system, method and tangible medium for unified exception handling with distributed exception identification includes a packet processing pipeline with at least two processing stages for processing data packets, each of the data packets being processed having an as... | 05/05/2009 |
| 7516303 | Field programmable gate array and microcontroller system-on-a-chip A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherei... | 04/07/2009 |
| 7447874 | Method and system for designing a flexible hardware state machine Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the p... | 11/04/2008 |
| 7426500 | Parallel computer architecture of a cellular type, modifiable and expandable This processing is distributed among number of simple hexagonal units distributed in a honeycomb layer, consisting of a central hexagram surrounded by six receiving cells, each representing an invariable binary place fed into central hexagram's CPU controlled by a s... | 09/16/2008 |
| 7424417 | System and method for clock domain grouping using data path relationships A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of ea... | 09/09/2008 |
| 7401333 | Array of parallel programmable processing engines and deterministic method of operating the same The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least some threads communicate with each other through communication objects e... | 07/15/2008 |
| 7373481 | Distributed-structure-based parallel module structure and parallel processing method A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1 independent flow-sequences is created, and the N+1 flow-sequences con... | 05/13/2008 |
| 7373567 | System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA A system and method of providing error detection and correction capability in an IC using redundant logic cells and an embedded field programmable gate array (FPGA). The system and method provide error correction (EC) to enable a defective logic function implemented... | 05/13/2008 |
| 7370167 | Time slicing device for shared resources and method for operating the same Broadly speaking, a device for addressing a shared resource is disclosed. The device includes at least one register in communication with the shared resource. The at least one register is configured to hold an address that is to be provided to the shared resource up... | 05/06/2008 |
| 7366842 | Creating permanent storage on the fly within existing buffers A circular buffer having an active cache window can be configured to temporarily allocate one or more locations in the active cache as permanent memory locations to eliminate the possibility of overwriting the contents of the permanent memory locations. The cache wi... | 04/29/2008 |
| 7357643 | Card connector assembly adapted for use with different wireless module cards A card connector assembly is adapted for use with a plurality of different wireless module cards, and a SIM card, and includes a first card connector mounted on a side of a circuit board and adapted to be connected electrically to a motherboard of a portable compute... | 04/15/2008 |
| 7359974 | System and method for dynamically controlling aggregate and individual packet flow characteristics within a compressed logical data tunnel A system and method for dynamically controlling aggregate and individual packet flow characteristics within a compressed logical data tunnel. A logical data tunnel is formed and includes one or more packet flows. Each packet flow includes individual packets having a... | 04/15/2008 |
| 7360065 | Synchronous network traffic processor A synchronous network traffic processor that synchronously processes, analyzes and generates data for high-speed network protocols, on a wire-speed, word-by-word basis. The synchronous network processor is protocol independent and may be programmed to convert protoc... | 04/15/2008 |
| 7352710 | Symmetrical codec selection in an asymmetrical codec environment A codec selector, and a corresponding method for establishing media channels between a local endpoint and a remote endpoint, are disclosed. The codec selector and method are useful with a media endpoint that is constrained to have matching transmit and receive codec... | 04/01/2008 |
| 7350238 | Data transfer system, data transfer apparatus, data-recording apparatus, data management method and identifier generation method A data transfer system provided by the present invention is capable of executing proper management of content transfers with a high degree of efficiency. In a data transfer apparatus employing a primary recording medium, rights to transfer contents stored in a prima... | 03/25/2008 |
| 7343482 | Program subgraph identification There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions corresponding to computational subgraphs identified within said pro... | 03/11/2008 |
| 7340509 | Reconfigurable appliance control system A reconfigurable appliance control system includes a dedicated appliance control (DAC) for controlling operation of an appliance. The system further includes an appliance communication control (ACC) for communicating with at least one appliance. The system includes ... | 03/04/2008 |
| 7340585 | Method and system for fast linked processor in a system on a chip (SoC) A fast linked multiprocessor network (22) including a plurality of processing modules (24, 26, 28, 30, 32, and 34) implemented on a field programmable gate array (10) and a plurality of configurable uni-directional links (21, 23, 25, 2... | 03/04/2008 |
| 7340583 | Method and apparatus of controlling memory device An address decoder 10 decodes an address signal 20 to generate access signals 22, 24. An OR circuit implements a logical OR of the signals 22, 24 to generate a chip enable signal. An address generation circuit 14 generates an addre... | 03/04/2008 |
| 7340587 | Information processing apparatus, microcomputer, and electronic computer An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch i... | 03/04/2008 |
| 7337301 | Designing configurable processor with hardware extension for instruction extension to replace searched slow block of instructions A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing har... | 02/26/2008 |
| 7333659 | Picture encoder and picture encoding method An encoder and an encoding method capable of improving the transfer efficiency in an encoding process is provided. The encoder determines the number of removed bit planes in order that the quantity of generated codes per frame is kept constant when performing the en... | 02/19/2008 |
| 7330481 | Highly channelized port polling in a telecommunications switch A method of telecommunication network switch port polling enables very highly channelized ports to be polled. A polling engine reads information from at least one of a plurality of poll registers, and each of the plurality of poll registers is associated with a uniq... | 02/12/2008 |
| 7318143 | Reuseable configuration data An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store opera... | 01/08/2008 |
| 7318080 | Split radix multiplication A first number is multiplied by a second number, by representing the first number as a first set of one or more W-bit wide numbers, and representing the second number as a second set of one or more W-bit wide numbers. Each of the W-bit wide numbers from the first se... | 01/08/2008 |
| 7318053 | Indexing system and method for nearest neighbor searches in high dimensional data spaces Vectors representing objects in n-dimensional space are approximated by local polar coordinates on partitioned cells of the data space in response to a query, e.g., a query data vector entered with a request to find âkâ nearest neighbors to the query vector. A s... | 01/08/2008 |
| 7313730 | Configuration logic for embedded software An integrated circuit such as an FPGA containing an embedded processor having test circuitry capable of controlling the processor's resources using JTAG commands includes a formatting circuit that formats soft data received from an external storage device into a JTA... | 12/25/2007 |
| 7310823 | Digital information recording apparatus and outputting apparatus A digital information recording apparatus includes multiple recording circuits for making multiple copies. The apparatus limits the number of copies, however, in accordance with copy information provided within the digital information itself. When the number of copi... | 12/18/2007 |
| 7308488 | Method, system and program products for distributing portal content processing The present invention generally relates to a method, system and program product for distributing portal content processing. Specifically, a request for portal content is received on a surrogate system and then passed to a portal system. The portal system will obtain... | 12/11/2007 |
| 7308560 | Processing unit A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for indicating independent data is supplied to the data computing unit. A da... | 12/11/2007 |
| 7305649 | Automatic generation of a streaming processor circuit A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of cir... | 12/04/2007 |
| 7299427 | Radio prototyping system A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at le... | 11/20/2007 |
| 7295994 | Information distribution system, terminal apparatus, information center, recording medium, and information distribution method When content data are distributed from an information center via a predetermined communication line to a terminal apparatus loaded with a recording medium recorded with its identifier and prepaid information, the information center manages the usable remaining amoun... | 11/13/2007 |
| 7293159 | Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction se... | 11/06/2007 |
| 7287148 | Unified shared pipeline allowing deactivation of RISC/DSP units for power saving An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and t... | 10/23/2007 |
