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Pillow with retractable umbrella
A pillow assembly having a supporting assembly and a retractable umbrella assembly that is easily transportable and allows a user to support his/her head while covering their face from sunlight.
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| Number | Title | Issue Date |
| 8176296 | Programmable microcontroller architecture Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming inform... | 05/08/2012 |
| 8060727 | Microprogrammed processor having mutiple processor cores using time-shared access to a microprogram control store There is provided a novel microprogrammed processor (100) by combining two or more processor cores (10) in such a way that the processor cores can share the special microprogram memory resource (20) that is located deep inside the processor arch... | 11/15/2011 |
| 8015392 | Updating instructions to free core in multi-core processor with core sequence table indicating linking of thread sequences for processing queued packets A method of updating execution instructions of a multi-core processor comprising receiving execution instructions at a processor including multiple programmable processing cores integrated on a single die, selecting subset of at least one of the cores, and loading a... | 09/06/2011 |
| 7917729 | System on chip IC with subsystem of multiple processing cores switch coupled to network protocol device and bus bridge to local system bus A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means con... | 03/29/2011 |
| 7877575 | Microprocessor The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of compo... | 01/25/2011 |
| 7865696 | Interface including task page mechanism with index register between host and an intelligent memory interfacing multitask controller A computing system that includes a number of processing elements, a memory and a multi-task controller is disclosed. The memory has an interface that includes a task page mechanism with an index register. A portion of the multi-task controller also has a task page r... | 01/04/2011 |
| 7792807 | Processing apparatus, data processing method, program for implementing the method, and storage medium A processing apparatus that is capable of dynamically updating a database when a processing device set for use is newly added, thus providing a process performed by the newly added processing device. In the processing apparatus, among a plurality of processing devic... | 09/07/2010 |
| 7552312 | Identifying messaging completion in a parallel computer by checking for change in message received and transmitted count at each node Methods, parallel computers, and products are provided for identifying messaging completion on a parallel computer. The parallel computer includes a plurality of compute nodes, the compute nodes coupled for data communications by at least two independent data commun... | 06/23/2009 |
| 7533245 | Hardware assisted pruned inverted index component An optimized document-indexing device is based on a pruned inverted index structure mapped to hardware. The device can be accommodated on a single chip and can be reprogrammed to accommodate index structures of different lengths and support varied posting-list sizes... | 05/12/2009 |
| 7490220 | Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used unti... | 02/10/2009 |
| 7426722 | Program code conversion for program code referring to variable size registers A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first ... | 09/16/2008 |
| 7415595 | Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between ... | 08/19/2008 |
| 7412588 | Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the packets to implement protocol conversion and generates converted pac... | 08/12/2008 |
| 7409680 | Program code conversion for a register-based program code A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first ... | 08/05/2008 |
| 7409251 | Method and system for writing NV memories in a controller architecture, corresponding computer program product and computer-readable storage medium The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding computer-readable storage medium, which may be used in particular to speed up writ... | 08/05/2008 |
| 7406584 | IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and receiving nodes each coupled by a communication channel. Individual c... | 07/29/2008 |
| 7389391 | Memory disposition methods and systems A memory disposition system, comprising a first memory device and a second memory device. First and second memory devices are provided to a system, such as an embedded system. The first and the second memory devices are coupled to a control unit, such as micro contr... | 06/17/2008 |
| 7379418 | Method for ensuring system serialization (quiesce) in a multi-processor environment A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies ... | 05/27/2008 |
| 7380037 | Data transmitter between external device and working memory A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus. ... | 05/27/2008 |
| 7370191 | Method and device for playing compressed multimedia files in semi-power on state of a computer A method and device for playing compressed multimedia files in a semi-power on state of a computer is provided. A program is provided in the BIOS so that POST (Power On Self Test) is not performed after the power is turned on. The program directly initializes multim... | 05/06/2008 |
| 7366877 | Speculative instruction issue in a simultaneously multithreaded processor A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic sp... | 04/29/2008 |
| 7363625 | Method for changing a thread priority in a simultaneous multithread processor An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority... | 04/22/2008 |
| 7363466 | Microcomputer A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 | 04/22/2008 |
| 7363470 | System and method to prevent in-flight instances of operations from disrupting operation replay within a data-speculative microprocessor A microprocessor may include one or more functional units configured to execute operations, a scheduler configured to issue operations to the functional units for execution, and at least one replay detection unit. The scheduler may be configured to maintain state in... | 04/22/2008 |
| 7363474 | Method and apparatus for suspending execution of a thread until a specified memory access occurs Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. S... | 04/22/2008 |
| 7360008 | Enforcing global ordering through a caching bridge in a multicore multiprocessor system The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the system interconnect, processor requests, and processor request compl... | 04/15/2008 |
| 7360067 | Method and data processing system for microprocessor communication in a cluster-based multi-processor wireless network A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-proces... | 04/15/2008 |
| 7356832 | Security for network-connected vehicles and other network-connected processing environments A method and apparatus provide security for a network-connected vehicle (or other networked environment) in which a predefined set of permitted operations relating to protected resources can be initiated remotely from elsewhere in the network, while security is main... | 04/08/2008 |
| 7356810 | Program code conversion for program code referring to variable size registers A method for generating an intermediate representation of computer program code written for running on a programmable machine comprises: (i) generating a plurality of register objects for holding variable values to be generated by the program code; and (ii) generati... | 04/08/2008 |
| 7353362 | Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means con... | 04/01/2008 |
| 7346900 | Register-based program code conversion A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first ... | 03/18/2008 |
| 7340643 | Replay mechanism for correcting soft errors A processor is provided that implements a replay mechanism to recover from soft errors. The processor includes a protected execution unit, a check unit to detect errors in results generated by the protected execution unit, and a replay unit to track selected instruc... | 03/04/2008 |
| 7334031 | System and user interface supporting processing and activity management for concurrently operating applications A system and associated communication protocol enables network compatible applications to be integrated into any process involving concurrent operation of applications. A system for use in a first application concurrently operating together with a plurality of netwo... | 02/19/2008 |
| 7330964 | Microprocessor with independent SIMD loop buffer An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of instruction and a second type of instruction and a co-processor configured to execute the loop detected b... | 02/12/2008 |
| 7328431 | Program code conversion for a register-based program code A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first ... | 02/05/2008 |
| 7321368 | Electronic system and method for display using a decoder and arbiter to selectively allow access to a shared memory An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the... | 01/22/2008 |
| 7318131 | CPU-containing LSI, and optical disk device and LSI device with the same The present invention provides a CPU-containing LSI in which software stored in an external memory is incorporated partially into a RAM and thereby the capacity of the RAM to be used can be held down, and an optical disk device including the same. In the CPU-contain... | 01/08/2008 |
| 7318218 | System and method for processor thread for software debugging A system and method for using a processor thread as a debugger is presented. A computer system boots up and initiates a debugger thread. The debugger thread loads a robust, debugger operating system and executes the debugger operating system. Once the debugger threa... | 01/08/2008 |
| 7318144 | Apparatus and method for interconnecting a processor to co-processors using shared memory An apparatus and method for interfacing a processor to one or more co-processors interface provides a dual ported memory to be used as a message passing buffer between the processor and the co-processors. Both the processor and co-processors can connect asynchronous... | 01/08/2008 |
| 7315261 | Method for converting data from pixel format to bitplane format This invention efficiently converts normal pixel data into bit plane data. A sequence of pack, bitwise shuffle, masking, rotate and merging operations transform tile from pixel form to bit plane form. This enables downstream algorithms to read only the data for the ... | 01/01/2008 |
