Quotables
"Flight by machines heavier than air is unpractical and insignificant, if not utterly impossible."
Simon Newcomb, astronomer ; Said in 1902, less than two years before the first flight at Kitty Hawk
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8078837 | Hardware engine control apparatus having hierarchical structure A hardware engine control apparatus includes: a plurality of hardware engines (HWEs) connected by a control bus, each of the hardware engines executing a series of different kinds of processing; a host control device that outputs control commands for controlling ope... | 12/13/2011 |
| 8019972 | Digital signal processor having a plurality of independent dedicated processors A digital signal processor uses a number of independent sub-processors that may be controlled by a master programmable controller. For example, a specialized input processor may process input signals while a specialized output processor may process output signals. E... | 09/13/2011 |
| 7793076 | Digital signals processor having a plurality of independent dedicated processors A digital signal processor uses a number of independent sub-processors that may be controlled by a master programmable controller. For example, a specialized input processor may process input signals while a specialized output processor may process output signals. E... | 09/07/2010 |
| 7779230 | Data flow execution of methods in sequential programs Distant parallelization of sequential programs is obtained by making parallelization decisions at the boundaries between program methods (e.g., functions and sub-routines). Experimentation suggests that such a partitioning allows for large-scale parallelization with... | 08/17/2010 |
| 7689809 | Transparent return to parallel mode by rampoline instruction subsequent to interrupt processing to accommodate slave processor not supported by operating system A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of ope... | 03/30/2010 |
| 7424595 | System for managing circuitry of variable function information processing circuit and method for managing circuitry of variable function information processing circuit Configuration management information having circuit configuration information for altering a circuit configuration of an FPGA (12) is stored in a memory (13), the configuration management information according to information related to an instruction g... | 09/09/2008 |
| 7395410 | Processor system with an improved instruction decode control unit that controls data transfer between processor and coprocessor A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data o... | 07/01/2008 |
| 7380037 | Data transmitter between external device and working memory A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus. ... | 05/27/2008 |
| 7363095 | Audio processing system The invention relates to an audio processing system 1. In order to improve the audio processing, the system comprises at least one audio processing component 11, 12, 13 with a group of real-time functions 14 for processing audio data and a group... | 04/22/2008 |
| 7356733 | System and method for system firmware causing an operating system to idle a processor According to one embodiment, a method comprises system firmware instructing a system's operating system to idle a processor, and responsive to the instructing, the operating system idling the processor and returning control over the processor to the system firmware.... | 04/08/2008 |
| 7346051 | Slave device, master device and stacked device A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements... | 03/18/2008 |
| 7343362 | Low complexity classification from a single unattended ground sensor node Disclosed are a system and method of multi-modality sensor data classification and fusion comprising partitioning data stored in a read only memory unit on a sensor node using a low query complexity boundary-decision classifier, applying an iterative two-dimensional... | 03/11/2008 |
| 7343475 | Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction A processor including an integer processing unit and a data processing unit. The processor can be operated by a first instruction format or a second instruction format. The first instruction format includes only an instruction for the integer processing unit, and is... | 03/11/2008 |
| 7334086 | Advanced processor with system on a chip interconnect technology An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messagin... | 02/19/2008 |
| 7293159 | Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction se... | 11/06/2007 |
| 7281250 | Multi-thread execution method and parallel processor system With a single program divided into a plurality of threads A to C, at the execution of the threads in parallel to each other by a plurality of processors, determination is made of a forkability of a slave thread into other processor in response to a fork instruction ... | 10/09/2007 |
| 7281123 | Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second... | 10/09/2007 |
| 7272664 | Cross partition sharing of state information A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for t... | 09/18/2007 |
| 7272670 | Integrated multimedia system An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia p... | 09/18/2007 |
| 7237041 | Systems and methods for automatic assignment of identification codes to devices A system and method for automatically and uniquely assigning identification codes to a plurality of slave processors. A master processor having communication port is linked to a first slave processor, which, itself, has first and second communication ports. The firs... | 06/26/2007 |
| 7234011 | Advanced microcontroller bus architecture (AMBA) system with reduced power consumption and method of driving AMBA system In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by isolating loads on a bus signal transfer path requiring the signal transition... | 06/19/2007 |
| 7225320 | Control architecture for a high-throughput multi-processor channel decoding system A multi-processor unit includes a first domain for processing data according to first configuration information and having multiple first domain processors each connected to communication apparatus and each performing a different function of the first processing. Th... | 05/29/2007 |
| 7222218 | System and method for goal-based scheduling of blocks of code for concurrent execution A scheduler may be configured to schedule a plurality of blocks of concurrent code for multi-threaded execution. The scheduler may be configured to initiate multi-threaded execution of the blocks of concurrent code in an order determined by block-level performance c... | 05/22/2007 |
| 7203829 | Apparatus and method for initializing coprocessor for use in system comprised of main processor and coprocessor An apparatus and method for initializing a coprocessor for use in system comprised of a main processor and coprocessor. The apparatus can be provided with fewer required memory components, such as a NOR flash memory, by enabling a coprocessor to perform a booting fu... | 04/10/2007 |
| 7200701 | System and method for processing system management interrupts in a multiple processor system A system and method for processing system management interrupts in multiple processor systems is disclosed. In one embodiment, a method for processing a system management interrupt (SMI) in an information handling system including, for each processor, identifying wh... | 04/03/2007 |
| 7200741 | Microprocessor having main processor and co-processor There is provided a microprocessor system that can execute a specific set of instructions at a high speed while limiting the increase in size of the circuitry. The microprocessor system, which executes instructions described in a program, comprises a main processor ... | 04/03/2007 |
| 7194598 | System and method using embedded microprocessor as a node in an adaptable computing machine The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In a... | 03/20/2007 |
| 7185174 | Switch complex selectively coupling input and output of a node in two-dimensional array to four ports and using four switches coupling among ports A switching element for switchably coupling a two-dimensional array of circuit elements comprises an input, an output, means for switchably coupling the input to the output; a first input/output port, a second input/output port, a third input/output port, and a four... | 02/27/2007 |
| 7181601 | Method and apparatus for prediction for fork and join instructions in speculative execution A method and apparatus for enabling the speculative forking of a speculative thread is disclosed. In one embodiment, a speculative fork instruction is conditioned by the results of a fork predictor. The fork predictor may issue predictions as to whether or not a spe... | 02/20/2007 |
| 7159211 | Method for executing a sequential program in parallel with automatic fault tolerance The present invention provides system and methods for executing a sequential in parallel. Parallel procedures, specified in the program, are executed as parallel slave processes. A process when actually accessing a ‘synchronous object’ that does not contain the ... | 01/02/2007 |
| 7152125 | Dynamic master/slave configuration for multiple expansion modules A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of th... | 12/19/2006 |
| 7152169 | Method for providing power management on multi-threaded processor by using SMM mode to place a physical processor into lower power state A power management technique uses system management interrupt (SMI) to manage states of a processor that includes multiple logical processors. When the SMI is generated, the states of logical processors are verified. When all of the logical processors are idle, the ... | 12/19/2006 |
| 7137121 | Data-processing circuit and method for switching between application programs without an operating system A data-processing circuit includes first and second cooperating processors where one of the processors context switches between applications without running an operating system. In one implementation, the first processor operates under the control of an operating sy... | 11/14/2006 |
| 7133951 | Alternate set of registers to service critical interrupts and operating system traps A processor includes a set of general purpose registers that are used when executing generic tasks and a set of exception registers that is dedicated for servicing specific exceptions. When a task is interrupted with an asserted “fast” exception, the processor a... | 11/07/2006 |
| 7127594 | Multiprocessor system and program optimizing method A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information indicating the program control mode, a VLIW mode or a multithread mode, in a p... | 10/24/2006 |
| 7107367 | Method for efficient buffer tag allocation A method and mechanism for allocating transaction tags. A request queue includes a counter whose value is used to identify a corresponding tag of a plurality of unique tags. The queue is configured to increment the counter and use the current count value to index in... | 09/12/2006 |
| 7103639 | Method and apparatus for processing unit synchronization for scalable parallel processing The present invention flexibly manages the formation of a partition from a plurality of independently executing cells (discrete hardware entities comprising system resources) in preparation for the instantiation of an operating system instance upon the partition. Sp... | 09/05/2006 |
| 7096344 | Processor for improving instruction utilization using multiple parallel processors and computer system equipped with the processor The present invention provides a processor capable of carrying out a plurality of operation instructions simultaneously in one cycle which improves utilization of an instruction when carrying out a single operation instruction, and a system equipped with such a proc... | 08/22/2006 |
| 7096468 | Programmer/feeder system task linking program A task linking program is provided for using a computer for interacting with on-line and off-line programming systems to perform tasks related to programming microdevices. The program is secure in being capable of being setup only in an administrator mode where micr... | 08/22/2006 |
| 7082610 | Method and apparatus for exception handling in a multi-processing environment A method and apparatus for exception handling in a multi-processor environment are described. In an embodiment, a method for handling a number of exceptions within a processor in a multi-processing system includes receiving an exception within the processor, wherein... | 07/25/2006 |
