Quotables
"The wireless music box has no imaginable commercial value. Who would pay for a message sent to nobody in particular?"
David Sarnoff, American radio pioneer ; 1921
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| Number | Title | Issue Date |
| 8161268 | Performing an allreduce operation on a plurality of compute nodes of a parallel computer Methods, apparatus, and products are disclosed for performing an allreduce operation on a plurality of compute nodes of a parallel computer. Each compute node includes at least two processing cores. Each processing core has contribution data for the allreduce operat... | 04/17/2012 |
| 8140828 | Handling transaction buffer overflow in multiprocessor by re-executing after waiting for peer processors to complete pending transactions and bypassing the buffer There is disclosed a method and apparatus for handling transaction buffer overflow in a multi-processor system as well as a transaction memory system in a multi-processor system. The method comprises the steps of: when overflow occurs in a transaction buffer of one ... | 03/20/2012 |
| 8103856 | Performance monitoring for new phase dynamic optimization of instruction dispatch cluster configuration In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an interval is run to determine the optimal configuration, which is used unti... | 01/24/2012 |
| 8001360 | Method and software for partitioned group element selection operation A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the ... | 08/16/2011 |
| 7962720 | Distributed processing system, distributed processing method and computer program A distributed processing system includes at least two processing elements (100 and 200) which are mutually connected, and each processing element having at least a processing section, a memory section, and a communication section. A first processing se... | 06/14/2011 |
| 7913063 | System and method for performance based call distribution A first performance indicator associated with a first agent is received from a workforce management system. A second performance indicator associated with a second agent is also received from the workforce management system. The first agent and the second agent are ... | 03/22/2011 |
| 7840780 | Shared resources in a chip multiprocessor In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, depe... | 11/23/2010 |
| 7669036 | Direct path monitoring by primary processor to each status register in pipeline chained secondary processors for task allocation via downstream communication Resource management techniques in multi-processor systems are described. Embodiments include a multi-processor system having a primary processor for communication with pipelined secondary processors. The secondary processors include registers containing status infor... | 02/23/2010 |
| 7523293 | Spawn-join instruction set architecture for providing explicit multithreading The invention presents a unique computational paradigm that provides the tools to take advantage of the parallelism inherent in parallel algorithms to the full spectrum from algorithms through architecture to implementation. The invention provides a new processing a... | 04/21/2009 |
| 7506138 | Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the... | 03/17/2009 |
| 7454595 | Distributed processor allocation for launching applications in a massively connected processors complex A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute p... | 11/18/2008 |
| 7437534 | Local and global register partitioning technique A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the pluralit... | 10/14/2008 |
| 7401333 | Array of parallel programmable processing engines and deterministic method of operating the same The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least some threads communicate with each other through communication objects e... | 07/15/2008 |
| 7363432 | Method and apparatus for directory-based coherence with distributed directory management A system for cache coherency comprises a memory. The memory comprises a plurality of data items and a plurality of directory information items, each data item uniquely associated with one of the plurality of directory information items. Each of the plurality of data... | 04/22/2008 |
| 7362762 | Distributed packet processing with ordered locks to maintain requisite packet orderings Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite packet orderings when distributing packets to be processed to different p... | 04/22/2008 |
| 7363397 | System and method for DMA controller with multi-dimensional line-walking functionality A system and method for a DMA controller with multi-dimensional line-walking functionality is presented. A processor includes an intelligent DMA controller, which loads a line description that corresponds to a shape or line. The intelligent DMA controller moves thro... | 04/22/2008 |
| 7360024 | Multi-port integrated cache A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction p... | 04/15/2008 |
| 7356568 | Method, processing unit and data processing system for microprocessor communication in a multi-processor system A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Eac... | 04/08/2008 |
| 7356819 | Task distribution Methods, signals, devices and systems are provided for matching tasks with processing units. A region within a multi-faceted task space is allocated to a processing unit. A point in the multi-faceted task space is assigned to a task. The task is then associated with... | 04/08/2008 |
| 7352648 | Semiconductor memory At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction. The incomplete cell array is disposed closer to a signal control unit... | 04/01/2008 |
| 7350117 | Management of microcode lock in a shared computing resource In a power controller or other computing resource shared by multiple processors, an ID is written to the lock register, thereby designating a master processor. A timer is then initialized to count for a predetermined period. Periodically, the master processor transm... | 03/25/2008 |
| 7325221 | Logic system with configurable interface A core block with a highly configurable interface such that the interface of the core can be optimally configured for the system the core is integrated into. In one embodiment the method consists of defining a configurable interface with different configuration opti... | 01/29/2008 |
| 7321956 | Method and apparatus for directory-based coherence with distributed directory management utilizing prefetch caches A system for cache coherency comprises a memory. The memory comprises a plurality of data items and a plurality of directory information items, each data item uniquely associated with one of the plurality of directory information items. Each of the plurality of data... | 01/22/2008 |
| 7318218 | System and method for processor thread for software debugging A system and method for using a processor thread as a debugger is presented. A computer system boots up and initiates a debugger thread. The debugger thread loads a robust, debugger operating system and executes the debugger operating system. Once the debugger threa... | 01/08/2008 |
| 7316017 | System and method for allocatiing communications to processors and rescheduling processes in a multiprocessor system In a multiprocessor system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment. The sy... | 01/01/2008 |
| 7290112 | System and method for virtualization of processor resources A system and method for virtualization of processor resources is presented. A thread is created on a processor and the processor's local memory is mapped into an effective address space. In doing so, the processor's local memory is accessible by other processors, re... | 10/30/2007 |
| 7281118 | Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memor... | 10/09/2007 |
| 7275246 | Executing programs for a first computer architecture on a computer of a second architecture Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context... | 09/25/2007 |
| 7272632 | Distributed system and multiplexing control method for the system A distributed system of this invention forms multiplexing by n computers, and permits up to f computers to fail and halt. Respective computers exchange input candidates via an internal network B, and generate lists of input candidates. Each computer repeats generati... | 09/18/2007 |
| 7269463 | Plant operating apparatus and method In a CRT operation system for operation and monitoring of plant equipment in a plant worksite through a central control room and a network, an operation control personal computer is provided for monitoring and operating the plant equipment, and one or more wireless ... | 09/11/2007 |
| 7260596 | Distributed service provider A station for a network apparatus, which includes interconnected by a communication link, includes a network connection; a self assessment module operable to determine a current status of the station including a measure of the stations available resources; a trust l... | 08/21/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7254736 | Systems and method providing input/output fencing in shared storage environments Systems and methods for I/O fencing in a shared storage environment are provided. Prior to initiating an I/O request, when feasible, the current time from a local timer is compared to the current state of an interval obtained for the target device. As a result, a de... | 08/07/2007 |
| 7251594 | Execution time modification of instruction emulation parameters To improve computer performance, problems of emulation such as WAR hazard, uneven utilization of machine resources, unnecessary dependencies, wasted hardware resources and data buffer pollution, are alleviated by responding to dynamic execution information, such as ... | 07/31/2007 |
| 7240182 | System and method for providing a persistent function server A system and method for providing a persistent function server is provided. A multi-processor environment uses an interface definition language (idl) file to describe a particular function, such as an “add” function. A compiler uses the idl file to generate sour... | 07/03/2007 |
| 7240277 | Memory error detection reporting A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing... | 07/03/2007 |
| 7240137 | System and method for message delivery across a plurality of processors A system and method is provided to deliver messages to processors operating in a multi-processing environment. In a multi-processor environment, interrupts are managed by storing events in a queue that correspond to a particular support processor. A main processor d... | 07/03/2007 |
| 7237068 | Computer system employing bundled prefetching and null-data packet transmission Various embodiments of a computer system employing bundled prefetching are disclosed. In one embodiment, a cache memory subsystem implements a method for prefetching data. The method comprises the cache memory subsystem receiving a read request to access a line of d... | 06/26/2007 |
| 7236971 | Method and system for deriving data through interpolation in a database system A database system is capable of performing interpolation (e.g., temporal interpolation) of data in response to receiving a database query. In one implementation, the database query contains an interpolation function. The database system in one example configuration ... | 06/26/2007 |
| 7228404 | Managing instruction side-effects A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the represe... | 06/05/2007 |
