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| Number | Title | Issue Date |
| 8190857 | Deleting a shared resource node after reserving its identifier in delete pending queue until deletion condition is met to allow continued access for currently accessing processor A method accelerates access of a multi-core system to its critical resources, which includes preparing to delete a critical node in a critical resource, separating the critical node from the critical resource, and deleting the critical node if the conditions for del... | 05/29/2012 |
| 8185720 | Processor block ASIC core for embedding in an integrated circuit A hardwired core is embedded in an integrated circuit having programmable circuitry. The hardwired core has a microprocessor; a crossbar interconnect coupled to processor local buses of the microprocessor; and a memory controller interface coupled to the crossbar in... | 05/22/2012 |
| 8180999 | Vertically tiered horizontally expandable micro grid system with bridge docking bay contoured by radial arms extending from central hub for coupling processor or power hubs A micro grid apparatus and associated method of formation. At least one tier in a printed circuit board is formed. Each tier includes complex shapes interconnected by bridge modules. Each complex shape includes a central area and at least three radial arms external ... | 05/15/2012 |
| 8156313 | Chained operation of functional units in integrated circuit by writing DONE/complete value and by reading as GO/start value from same memory location In an embodiment, the present invention discloses a flexible and reconfigurable architecture with efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the output of... | 04/10/2012 |
| 8122228 | Broadcasting collective operation contributions throughout a parallel computer Methods, systems, and products are disclosed for broadcasting collective operation contributions throughout a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node h... | 02/21/2012 |
| 8103855 | Linking functional blocks for sequential operation by DONE and GO components of respective blocks pointing to same memory location to store completion indicator read as start indicator The present disclosure provides a methodology for reducing congestion of a processing unit, preferably by configuring a plurality of functional blocks to run in parallel or in series without the influence or input from the processing unit. In an embodiment, the pres... | 01/24/2012 |
| 8074054 | Processing system having multiple engines connected in a daisy chain configuration A processing system includes a group of processing units (“PUs”) arranged in a daisy chain configuration or a sequence capable of parallel processing. The processing system, in one embodiment, includes PUs, a demultiplexer (“demux”), and a multiplexer (“mu... | 12/06/2011 |
| 8065503 | Iteratively processing data segments by concurrently transmitting to, processing by, and receiving from partnered process Methods, systems and computer programs for distributing a computing operation among a plurality of processes and for gathering results of the computing operation from the plurality of processes are described. An exemplary method includes the operations of pairing a ... | 11/22/2011 |
| 8037284 | Stream processing in optically linked super node clusters of processors by mapping stream graph to nodes and links A stream processing computer architecture includes creating a stream computer processing (SCP) system by forming a super node cluster of processors representing physical computation nodes (“nodes”), communicatively coupling the processors via a local interconnec... | 10/11/2011 |
| 8032821 | Multi-thread spreadsheet processing with dependency levels This disclosure relates to a method and system of processing chain calculations in spreadsheet applications utilizing multiple processors, each having a separate recalculation engine. A single calculation chain may be reordered into a unified chain where supporting ... | 10/04/2011 |
| 8027972 | Nodal data normalization Embodiments of the invention may be used to normalize data stored in an in-memory database on a parallel computer system. The data normalization may be used to achieve memory savings, thereby reducing the number of compute nodes required to store an in-memory databa... | 09/27/2011 |
| 7996653 | Shared resources in a chip multiprocessor In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, depe... | 08/09/2011 |
| 7971029 | Barrier synchronization method, device, and multi-core processor A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when ... | 06/28/2011 |
| 7953957 | Mapping and distributing parallel algorithms to compute nodes in a parallel computer based on temperatures of the compute nodes in a hardware profile and a hardware independent application profile describing thermal characteristics of each parallel algorithm Methods, apparatus, and products for distributing parallel algorithms of a parallel application among compute nodes of an operational group in a parallel computer are disclosed that include establishing a hardware profile, the hardware profile describing thermal cha... | 05/31/2011 |
| 7941637 | Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a... | 05/10/2011 |
| 7917728 | Integrated circuit and method for transaction retraction An integrated circuit having a plurality of processing modules (I, T) is provided. At least one first processing module (I) issues at least one transaction towards at least one second processing module (T). Said integrated circuit further comprises at least one firs... | 03/29/2011 |
| 7908462 | Virtual world simulation systems and methods utilizing parallel coprocessors, and computer program products thereof The current invention provides a virtual world simulation system capable of hosting with massive amount of concurrent players by integrating commodity parallel co-processors into servers. The current invention proposes novel parallel processing algorithms to make us... | 03/15/2011 |
| 7895413 | Microprocessor including register renaming unit for renaming target registers in an instruction with physical registers in a register sub-file A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storin... | 02/22/2011 |
| 7849289 | Distributed memory type information processing system In parallel computers, sorting and calculation of large-scale data are realized while large-scale data is held in the respective processors without sharing the large-scale data between the processors so as to reduce communication between the processors. An informati... | 12/07/2010 |
| 7788242 | Method and system for implementing a concurrent set of objects A method for inserting an object into a concurrent set including obtaining a key associated with the object, traversing the concurrent set using a first thread containing the key, identifying a first insertion point while traversing the concurrent set, where the fir... | 08/31/2010 |
| 7694107 | Dynamic performance ratio proportionate distribution of threads with evenly divided workload by homogeneous algorithm to heterogeneous computing units In at least some embodiments, a system, comprises a first computing unit having a first type of processors. The system further comprises a second computing unit having a second type of processors, the second computing unit being coupled to the first computing unit. ... | 04/06/2010 |
| 7627738 | Request and combined response broadcasting to processors coupled to other processors within node and coupled to respective processors in another node A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for communication, and the second processing node includes a plurality of second pr... | 12/01/2009 |
| 7600095 | Executing scatter operation to parallel computer nodes by repeatedly broadcasting content of send buffer partition corresponding to each node upon bitwise OR operation Executing a scatter operation on a parallel computer includes: configuring a send buffer on a logical root, the send buffer having positions, each position corresponding to a ranked node in an operational group of compute nodes and for storing contents scattered to ... | 10/06/2009 |
| 7581081 | Systems and methods for software extensible multi-processing A system for processing applications includes processor nodes and links interconnecting the processor nodes. Each node includes a processing element, a software extensible device, and a communication interface. The processing element executes at least one of the app... | 08/25/2009 |
| 7516301 | Multiprocessor computing systems with heterogeneous processors Heterogeneous processors can cooperate for distributed processing tasks in a multiprocessor computing system. Each processor is operable in a “compatible” mode, in which all processors within a family accept the same baseline command set and produce identical re... | 04/07/2009 |
| 7490219 | Counter counts valid requests based on a judgment in a system having a plurality of pipeline processors In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register provided at the final stage of a pipeline register in a stage in which the ... | 02/10/2009 |
| 7441106 | Distributed processing in a multiple processing unit environment Method and apparatus for performing distributed processing in a multi-processing unit environment. A first processing unit modifies a complex operation to provide an operational request packet comprising a corresponding simplex operation and remainder. The packet is... | 10/21/2008 |
| 7436559 | Load assignment in image processing by parallel processing In image processing carried out by means of repeated execution of process set which includes N unit processes (where N is an integer equal to 3 or greater), prior to execution of the process groups, the N unit processes are assigned to a number M (where M is an inte... | 10/14/2008 |
| 7428210 | Fail over method and a computing system having fail over function Loads on a plurality of computers are made uniform after a fail over, and resource competition is prevented. Loads of nodes (1 to 4) in a cluster (100) are obtained, taking-over information when a trouble occurs in one of the plurality of nodes ... | 09/23/2008 |
| 7426500 | Parallel computer architecture of a cellular type, modifiable and expandable This processing is distributed among number of simple hexagonal units distributed in a honeycomb layer, consisting of a central hexagram surrounded by six receiving cells, each representing an invariable binary place fed into central hexagram's CPU controlled by a s... | 09/16/2008 |
| 7426182 | Method of managing signal processing resources A method of setting up a new call in a signal processor includes selecting a signal processor that has sufficient bandwidth to open a new channel while assuming that the new channel and any open but unestablished channels on the signal processor require more than a ... | 09/16/2008 |
| 7424581 | Host memory interface for a parallel processor A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing elements. The processing elements transfer data to and from the memory at the... | 09/09/2008 |
| 7415595 | Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between ... | 08/19/2008 |
| 7401333 | Array of parallel programmable processing engines and deterministic method of operating the same The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least some threads communicate with each other through communication objects e... | 07/15/2008 |
| 7398368 | Atomic operation involving processors with different memory transfer operation sizes Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address conta... | 07/08/2008 |
| 7395082 | Method and system for handling events in an application framework for a wireless device Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI wireless framework. An identity of the acquired MMI event may be deter... | 07/01/2008 |
| 7386619 | System and method for allocating communications to processors in a multiprocessor system In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a locking mechanism specific to the resources required for assignment. ... | 06/10/2008 |
| 7386714 | Transmitting data from a single storage unit between multiple processors during booting An electronic control unit includes a main microcomputer and a sub-microcomputer. Both the microcomputers include buffers for initialization and buffers for normal processing. At the time of startup of the main microcomputer and the sub-microcomputer, the sub-microc... | 06/10/2008 |
| 7383423 | Shared resources in a chip multiprocessor In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured to return a first value in response to the first read operation, depe... | 06/03/2008 |
| 7380039 | Apparatus, method and system for aggregrating computing resources A system for executing applications designed to run on a single SMP computer on an easily scalable network of computers, while providing each application with computing resources, including processing power, memory and others that exceed the resources available on a... | 05/27/2008 |
