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| Number | Title | Issue Date |
| 7406653 | Anomaly detection based on directional data Properly detects an anomaly on the basis of directional data that are obtained in sequence from a monitored object. An anomaly detecting method includes: sequentially generating directional data indicating a feature of each piece of monitored data correspondingly to... | 07/29/2008 |
| 7398301 | Method and apparatus for facilitating distributed delivery of content across a computer network One embodiment of the present invention provides a system that facilitates receiving content at a client from one or more servers that can potentially provide the content. The client starts by sending a request for the content to a directory server. In response to t... | 07/08/2008 |
| 7376890 | Method and system for checking rotate, shift and sign extension functions using a modulo function A method of discovering a fault in a circuit is disclosed. The method comprises generating a first result of a selected function by performing the selected function on an operand, wherein the selected function employs a mask. Once the function is performed, an antim... | 05/20/2008 |
| 7370182 | Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing un... | 05/06/2008 |
| 7337443 | Method and apparatus for processing program threads A procedure identifies a program image and generates a basic block flow graph associated with the program image. Execution of the program image is benchmarked and the basic block flow graph is annotated with the results of the benchmarking of the program image. Basi... | 02/26/2008 |
| 7325079 | Information terminal, information processing system, and methods of controlling the same An information terminal disclosed herein includes a data storage in which data is stored; an internal controller which accesses the data storage by a request from inside the information terminal; and an external controller which accesses the data storage by a reques... | 01/29/2008 |
| 7280539 | Data driven type information processing apparatus In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a funct... | 10/09/2007 |
| 7278013 | Apparatus having a cache and a loop buffer Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core. ... | 10/02/2007 |
| 7266671 | Register addressing There is disclosed a technique for accessing a register file which comprises defining a first register address as a plurality of bits and using said first register address to access said register file generating a second register address by using a sequence of said ... | 09/04/2007 |
| 7240169 | Protocol for coordinating the distribution of shared memory Methods, systems, and articles of manufacture consistent with the present invention coordinate distribution of shared memory to threads of control executing in a program by using a cooperative synchronization protocol. The protocol serializes access to memory by com... | 07/03/2007 |
| 7237041 | Systems and methods for automatic assignment of identification codes to devices A system and method for automatically and uniquely assigning identification codes to a plurality of slave processors. A master processor having communication port is linked to a first slave processor, which, itself, has first and second communication ports. The firs... | 06/26/2007 |
| 7236456 | Using shadow Mcast/Bcast/Dlf counter and free pointer counter to balance unicast and Mcast/Bcast/Dlf frame ratio A network device for managing data flow can have at least one receiving port configured to receive data, a first counter configured to monitor at least one pointer, and a second counter configured to record the at least one pointer to correspond to the at least one ... | 06/26/2007 |
| 7222193 | Computer network payment system A method of electronic payment for data transferred across a computer network from a server to a client by means of at least one router which forwards data. An electronic data request is sent from the client to the server via one or more routers. The server then sen... | 05/22/2007 |
| 7188047 | System and methods for providing histogram computation in a high precision rasterization data pipeline A system and methods for implementing histogram computation, for example, into the rasterization pipeline of a 3-D graphics system, are provided. With the histogram computation mechanism, statistical histogram data may be generated for input data of any kind or retr... | 03/06/2007 |
| 7174525 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparat... | 02/06/2007 |
| 7142214 | Data format for low power programmable processor A graphics processor includes programmable arithmetic logic units (ALUs) for performing scalar arithmetic operations on pixel packets. For a selected scalar arithmetic operation, operands in pixel packets may be formatted in a S1.8 format to improve dynamic range. F... | 11/28/2006 |
| 7130986 | Determining if a register is ready to exchange data with a processing element According to some embodiments, it is determined if a register is ready to exchange data with a processing element. ... | 10/31/2006 |
| 7124280 | Execution control apparatus of data driven information processor for instruction inputs An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that stores N (N≧2) waiting data and respective data valid flags in one addr... | 10/17/2006 |
| 7106210 | Method and apparatus for mud pulse telemetry A method and related apparatus for telemetry between downhole devices and surface devices. In particular, the methods and related apparatus may send a first datum of a first parameter in an uncompressed form, and send a second datum of the first parameter in compres... | 09/12/2006 |
| 7100025 | Apparatus and method for performing single-instruction multiple-data instructions An apparatus and method for performing single-instruction multiple-data instructions using a single multiply-accumulate unit while minimizing operational latency. The multiply-accumulate unit generates a first half and a second half of a data result. A register stor... | 08/29/2006 |
| 7093109 | Network processor which makes thread execution control decisions based on latency event lengths A control mechanism is established between a network processor and a tree search coprocessor to deal with latencies in accessing the data such as information formatted in a tree structure. A plurality of independent instruction execution threads are queued to enable... | 08/15/2006 |
| 7089405 | Index-based scoreboarding system and method A computer system includes a scoreboard mechanism that provides a locking scheme to preserve data dependencies. An index is used to unlock (i.e., invalidate) scoreboard entries when a terminating event associated with that entry's instruction has occurred. For a loa... | 08/08/2006 |
| 7047395 | Reordering serial data in a system with parallel processing flows A distributed system is provided for apportioning an instruction stream into multiple segments for processing in multiple parallel processing units, and for merging the processed segments into a single processed instruction stream having the same sequential relative... | 05/16/2006 |
| 7039906 | Compiler for enabling multiple signed independent data elements per register A compiler for data processing outputs lower-level code for packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and when executed, the code simultaneously operates on the elements in a register in a singl... | 05/02/2006 |
| 7035996 | Generating data type token value error in stream computer A stream computer comprises a plurality of interconnected functional units. The functional units are responsive to a data- stream containing data and tokens. The data is to be operated on by one or more of the plurality of interconnected functional units. Dig... | 04/25/2006 |
| 7035989 | Adaptive memory allocation This functions maintains two trees: a fast access tree referring to memory blocks of a size most often requested, and a general access tree referring to memory blocks of a size less often requested. After satisfying a request for a memory block, the function adjusts... | 04/25/2006 |
| 7032098 | Data-driven type information processing apparatus and information processing method allowing for effective use of memory A data-driven type information processing apparatus includes at least a paired data generating unit, a memory control unit, and data memory. The memory control unit includes a pipeline register receiving a data packet output from the paired data generating unit, inc... | 04/18/2006 |
| 7020148 | Data transferring apparatus and data transferring method that use fast ring connection A data transferring apparatus includes a ring bus, which circularly transfers data by holding in a slot to one direction and a plurality of nodes connected to the ring bus. Each of the plurality of nodes includes a detector and a controller. The detector detects whe... | 03/28/2006 |
| 7003648 | Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU A multi-threaded processor provides for efficient flow-control from a pool of un-executed stores in an instruction queue to a store queue. The processor also includes similar capabilities with respect to load instructions. The processor includes logic organized into... | 02/21/2006 |
| 6976150 | Resource flow computing device A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable pro... | 12/13/2005 |
| 6954843 | Data driven information processor capable of internally processing data in a constant frequency irrespective of an input frequency of a data packet from the outside A packet generation unit divides a plurality of generated clocks to generate clocks with different frequencies, selects any of the frequencies, sets destination information and data depending on a selected clock rate and generates a data packet that stores the setti... | 10/11/2005 |
| 6950963 | Control method and apparatus for testing of multiple processor integrated circuits and other digital systems An integrated circuit or other type of digital system including multiple processors is tested using a control mechanism which dynamically defines a group of processors subject to common control. The control mechanism receives one or more commands for each of the pro... | 09/27/2005 |
| 6941448 | Data-driven processor having multiple-precision data processing function and data processing method thereof When a prescribed operation is performed on 1024-bit multiple-precision data in a data-driven processor, the multiple-precision data is treated as a plurality of single-precision data obtained by dividing the multiple-precision data by every 32 bits in accordance wi... | 09/06/2005 |
| 6904511 | Method and apparatus for register file port reduction in a multithreaded processor Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor thread, and utilizes at least a portion of the thread identifier to select ... | 06/07/2005 |
| 6792522 | Data driven information processor carrying out processing using packet stored with plurality of operand data In a data driven information processor, an operation apparatus includes a data select unit and a flag select unit selecting information according to the value of flag data in an input data packet. The data select unit selects the processed result for each data in th... | 09/14/2004 |
| 6782521 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparat... | 08/24/2004 |
| 6757817 | Apparatus having a cache and a loop buffer Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core. ... | 06/29/2004 |
| 6754807 | System and method for managing vertical dependencies in a digital signal processor An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of retired identifiers associated with retired instructions and for determi... | 06/22/2004 |
| 6711665 | Associative processor An associative processor includes a plurality of arrays of content addressable memory (CAM) cells and a plurality of tags registers in a tags logic block. Different tags registers are associated with different CAM cell arrays at will, to support parallel execution o... | 03/23/2004 |
| 6625146 | Method and apparatus for operating a network switch in a CPU-less environment A method and apparatus are disclosed for operating a network switch without the use of a CPU. A control interface is used to connect the network switch to the external CPU. The control interface generates an initialization signal indicative of the absence... | 09/23/2003 |
