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| Number | Title | Issue Date |
| 8074053 | Dynamic instruction and data updating architecture A memory update engine provides flexible modification of data in memory. A processor may employ the update engine to update filter coefficients, special effects parameters, signal sample processing instructions, or any other instruction or data during processing. Th... | 12/06/2011 |
| 7827386 | Controlling memory access devices in a data driven architecture mesh array A first set of instructions and incoming data are provided to a first processing unit of a data driven processor, to operate upon the incoming data. The first processing unit, in response to recognizing that the first set of instructions will require either reading ... | 11/02/2010 |
| 7493469 | Performance evaluation apparatus, performance evaluation method, program and computer readable recording medium From an application program described in the form of a flow graph, input and output arcs are extracted. Packet rates on the input and output arcs are extracted, and it is determined whether the packet rates of the input arc and the output arc are lower than an upper... | 02/17/2009 |
| 7490218 | Building a wavecache A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called “WaveScalar.” WaveScalar is a compiler tha... | 02/10/2009 |
| 7406685 | System and method for whole-system program analysis Defect detection in a software system made of multiple computer program programs is facilitated by using information about cross-program interactions and dependency relationships between programs to analyze the individual programs in such a way that the behavior of ... | 07/29/2008 |
| 7383425 | Massively reduced instruction set processor This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video... | 06/03/2008 |
| 7373481 | Distributed-structure-based parallel module structure and parallel processing method A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1 independent flow-sequences is created, and the N+1 flow-sequences con... | 05/13/2008 |
| 7373485 | Clustered superscalar processor with communication control between clusters A clustered superscalar processor for reducing the miss rate of a register cache and reducing the possibility of miss penalties. The processor checks before storing an instruction in an instruction window whether there is a data dependency relationship between the i... | 05/13/2008 |
| 7363559 | Detection of tap register characteristics According to some embodiments, first data including a token is shifted into an IEEE 1149.1-compliant shift register and second data is received, the second data being shifted out from the IEEE 1149.1-compliant shift register as a result of the shifting of the first ... | 04/22/2008 |
| 7360065 | Synchronous network traffic processor A synchronous network traffic processor that synchronously processes, analyzes and generates data for high-speed network protocols, on a wire-speed, word-by-word basis. The synchronous network processor is protocol independent and may be programmed to convert protoc... | 04/15/2008 |
| 7356026 | Node translation and protection in a clustered multiprocessor system A method of node translation for communicating over virtual channels in a clustered multiprocessor system using connection descriptors (CDs), which specify the endpoint nodes for virtual connections. The system includes a local processing element node, a remote proc... | 04/08/2008 |
| 7340586 | Data transfer for debugging in data driven type processor processing data packet with data flow program including transfer control bit setting instruction A data-driven type information processor includes a ifinction processor manipulating contents in a data packet, a program storage unit storing a data flow program used by the function processor, and a branch unit controlling data flow whether to allow flow of a data... | 03/04/2008 |
| 7324540 | Network protocol off-load engines The disclosure describes techniques for coordinating operation of multiple network protocol off-load engines (e.g., Transport Control Protocol (TCP) off-load engines). ... | 01/29/2008 |
| 7325232 | Compiler for multiple processor and distributed memory architectures A compiler for multiple processor and distributed memory architectures is described. The compiler uses a high-level language to represent a task-level network of behaviors that describes an embedded system. The compiler maps a plurality of tasks and data onto a mult... | 01/29/2008 |
| 7321369 | Method and apparatus for synchronizing processing of multiple asynchronous client queues on a graphics controller device An apparatus and method are disclosed for synchronization of command processing from multiple command queues. Various embodiments employ a condition code register that indicates which queues should have processing suspended until a specified event condition occurs. ... | 01/22/2008 |
| 7318143 | Reuseable configuration data An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store opera... | 01/08/2008 |
| 7313672 | Intellectual property module for system-on-chip Disclosed is an IP module for an SOC which brings easiness in designing system architecture and integration. The IP module of the invention includes a controller for generating a control signal for IP module with reference to a handshake signal and sending a control... | 12/25/2007 |
| 7280539 | Data driven type information processing apparatus In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a funct... | 10/09/2007 |
| 7269718 | Method and apparatus for verifying data types to be used for instructions and casting data types if needed A method, apparatus, and computer instructions in a processor for performing arithmetic operations. A data type associated with a particular memory location is used to determine if an operation about to be performed on the data in that location is legal. If the oper... | 09/11/2007 |
| 7260707 | Variable length instruction pipeline A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to red... | 08/21/2007 |
| 7260706 | Branch misprediction recovery using a side memory A mispredicted path side memory is configured to be coupled to a stage in an instruction pipeline. As instructions advance through the pipeline, a result from the stage is stored into the mispredicted path side memory. The result is restored from the mispredicted pa... | 08/21/2007 |
| 7243345 | Multi-thread executing method and parallel processing system In a multi-thread executing method of dividing a single program into a plurality of threads and executing the program by a plurality of processors in parallel, at a time of every fork instruction of the executing thread, when there already exists a child thread gene... | 07/10/2007 |
| 7237089 | SIMD operation method and SIMD operation apparatus that implement SIMD operations without a large increase in the number of instructions An operation method has processing for applying a same type of operation in parallel to N M-bit operands to obtain N M-bit operation results executed on a computer. Here, N is an integer equal to or greater than 2 and M is an integer equal to or greater than 1. The ... | 06/26/2007 |
| 7234642 | Memory device A memory device operable to receive an input signal and to generate a corresponding data bearing output signal in response. The device includes a series of circuit stages operable to be triggered by the input signal at a first stage of the series, thereby causing a ... | 06/26/2007 |
| 7210128 | Event-driven observability enhanced coverage analysis A method for event-driven observability enhanced coverage analysis of a program parses a program into variables and data dependencies, wherein the data dependencies comprise assignments and operations. The method builds a data structure having multiple records, with... | 04/24/2007 |
| 7165150 | Restricting access to memory in a multithreaded environment Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support f... | 01/16/2007 |
| 7161828 | Asynchronous static random access memory A static random access memory (SRAM) is provided including a plurality of SRAM state elements and SRAM environment circuitry. The SRAM environment circuitry is operable to interface with external asynchronous circuitry and to enable reading of and writing to the SRA... | 01/09/2007 |
| 7155708 | Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation An embodiment of the invention includes a method of simulating a hybrid instruction processor and reconfigurable processor implemented algorithm which utilizes a runtime selectable emulation library that emulates a reconfigurable processor and its resources, and a c... | 12/26/2006 |
| 7148503 | Semiconductor device, function setting method thereof, and evaluation method thereof The present invention provides a semiconductor device, in which a plurality of chip IPs are mounted onto a common semiconductor circuit board, an evaluation method for the same, and a function setting method for the same. Various IP groups can be mounted as chip IPs... | 12/12/2006 |
| 7140017 | Performance of channels used in communicating between senders and receivers A plurality of batch lists are maintained by a channel in order to improve the efficiency of the channel in performing messaging between a sender and a receiver. For example, a Next Batch list is used to prefetch messages to be sent to the receiver from the sender; ... | 11/21/2006 |
| 7130986 | Determining if a register is ready to exchange data with a processing element According to some embodiments, it is determined if a register is ready to exchange data with a processing element. ... | 10/31/2006 |
| 7130987 | Reconfigurable semantic processor Data processors and methods for their configuration and use are disclosed. As opposed to traditional von Neumann microprocessors, the disclosed processors are semantic processors—they parse an input stream and direct one or more semantic execution engines to execu... | 10/31/2006 |
| 7127589 | Data processor A data processor capable of executing sequential processing efficiently while retaining the advantages of a prior art data-driven processor. The data processor includes: an instruction fetch unit which fetches a data-driven instruction or a control-driven instructio... | 10/24/2006 |
| 7127522 | Message multicast method and computer To provide a message sending function which reflects “taste” in a destination agent designated by a user and a policy of the market in which agents operate. When multicasting a message to agents, a message monitor executes the steps of: receiving preferential de... | 10/24/2006 |
| 7124280 | Execution control apparatus of data driven information processor for instruction inputs An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that stores N (N≧2) waiting data and respective data valid flags in one addr... | 10/17/2006 |
| 7120903 | Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated... | 10/10/2006 |
| 7117344 | Processor execution, pipeline sharing instruction, and data source path A processor execution pipeline that includes, a stage latch circuit and a stage latch circuit provided at an input stage of a first processing stage for holding a first processing data SOURCE1 and a second processing data, respectively; an operator provid... | 10/03/2006 |
| 7114086 | System for reduced power consumption by monitoring instruction buffer and method thereof A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated with an instruction buffer is monitored to determine whether power consumption modes can be initiated within a system. If a number of p... | 09/26/2006 |
| 7107258 | Search engine for large database search using CAM and hash A search engine having a controller, a memory, and at least one hash-CAM (H-CAM). The memory includes a database of search values and associate content or just associate content. The controller uses search values to access the memory to obtain the search results. Th... | 09/12/2006 |
| 7100133 | Computer system and method to dynamically generate system on a chip description files and verification information The present invention facilitates automation of system on a chip (SoC) design, manufacture and verification in a convenient and efficient manner. In one embodiment, a SoC netlist builder and verification computer system of the present invention includes a user inter... | 08/29/2006 |
