Bizarre Patents
Dining Table Having Integral Dishwasher
A space-saving dishwasher, which may be installed within a counter top or table, having a dish-carrying rack that is vertically shiftable through the open top of the dishwasher for facilitating loading and unloading of the dishes.
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| Number | Title | Issue Date |
| 7418583 | Data dependency detection using history table of entry number hashed from memory address A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence... | 08/26/2008 |
| 7398376 | Instructions for ordering execution in pipelined processes Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory write operations local to a CPU to occur in an arbitrary order, and plac... | 07/08/2008 |
| 7386710 | Methods and apparatus for scalable array processor interrupt detection and response Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable ... | 06/10/2008 |
| 7366879 | Alteration of functional unit partitioning scheme in multithreaded processor based upon thread statuses A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor.... | 04/29/2008 |
| 7363467 | Dependence-chain processing using trace descriptors having dependency descriptors An apparatus and method for a processor microarchitecture that quickly and efficiently takes large steps through program segments without fetching all intervening instructions. The microarchitecture processes descriptors of trace sequences in program order so as to ... | 04/22/2008 |
| 7313645 | Processor to reduce data rearrangement instructions for matrices in multiple memory banks The present invention provides a processor including: a plurality of memory banks; a read-address generation circuit for supplying a read address to each of the memory banks on the basis of a read-register specification and a read-register scan direction; a read con... | 12/25/2007 |
| 7305567 | Decoupled architecture for data ciphering operations In one embodiment, an apparatus comprises a microcontroller unit to store instructions into an execution queue. The apparatus also comprises an execution queue unit to generate a widely decoded functional execution instruction based on at least one instruction store... | 12/04/2007 |
| 7281123 | Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second... | 10/09/2007 |
| 7254689 | Decompression of block-sorted data In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a plurality of paths through a mapping array T are being handled by a pr... | 08/07/2007 |
| 7254807 | Program conversion apparatus, program conversion method, and computer program for executing program conversion process A compiling unit (110) generates indefinite branch information showing that an instruction set to be selected is indefinite, instead of generating a branch instruction. A linking unit (130) generates an appropriate direct addressing branch instruction ... | 08/07/2007 |
| 7254697 | Method and apparatus for dynamic modification of microprocessor instruction group at dispatch Dynamic reformatting of a dispatch group by selective activation of inactive Start bits of instructions within the dispatch group at the time the instructions are read from the IBUF. The number of instructions in the reformatted dispatch groups can vary from as few ... | 08/07/2007 |
| 7250953 | Statistics instrumentation for low power programmable processor A graphics processor includes a graphics pipeline having a set of tap points. A configurable test point selector monitors a selected subset of tap points and counts statistics for at least one condition associated with each tap point of the subset of tap points.... | 07/31/2007 |
| 7249252 | Method of replacing initialization code in a control store with main code after execution of the initialization code has completed A method includes loading initialization code into a control store in an embedded microprocessor and executing the initialization code. The method determines if the execution of the initialization code is complete and replaces the initialization code in the control ... | 07/24/2007 |
| 7245149 | Dynamic programmable logic array having enable unit A DPLA (dynamic programmable logic array) uses an enable unit for each output line that provides OR-functionality, to eliminate a clock signal in the OR-plane. A clock signal is used only in the AND-plane for pre-charging the product term lines. Such a DPLA operates... | 07/17/2007 |
| 7243345 | Multi-thread executing method and parallel processing system In a multi-thread executing method of dividing a single program into a plurality of threads and executing the program by a plurality of processors in parallel, at a time of every fork instruction of the executing thread, when there already exists a child thread gene... | 07/10/2007 |
| 7243206 | Method and apparatus for using a RAM memory block to remap ROM access requests A method and data processing apparatus for remapping selected data access requests issued by a processor for accessing data items stored on a ROM. The method comprises the following steps: storing at least one replacement data item corresponding to at least one data... | 07/10/2007 |
| 7231511 | Microinstruction pointer stack including speculative pointers for out-of-order execution Methods and apparatus, including computer program products, for a microinstruction pointer stack in a processor. A method executed in a processor includes executing microcode (μcode) addressed by pointers stored in an out-of-order microinstruction pointer (μIP) st... | 06/12/2007 |
| 7228392 | Wireless data communications using FIFO for synchronization memory A microprocessor system architecture is disclosed which allows for the selective execution of programmed ROM microcode or, alternatively, RAM microcode if there has been a correction or update made to the ROM microcode originally programmed into the system. Patched ... | 06/05/2007 |
| 7228536 | System for rewriting control program in vending machine The present invention provides a vending machine control program rewriting system that facilitates the rewriting of a control program in the vending machine. The vending machine comprises a communication controller which receives a new control program sent from a ho... | 06/05/2007 |
| 7225440 | System and method for manufacturing and updating insertable portable operating system module A method and system for storing a running image of an operating system on a removable operating system module. The module is first inserted into a first computer system. The operating system is installed on the first computer, an execution of the operating system is... | 05/29/2007 |
| 7225448 | System and method for hibernating application state data on removable module A method and system for hibernating the state of executing applications on a removable module and resuming the applications at later time using the saved applications' state. After inserting the removable module into a computer system, the applications' state inform... | 05/29/2007 |
| 7225281 | Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each b... | 05/29/2007 |
| 7216220 | Microprocessor with customer code store A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not subject to eviction and the like, as a cache memory would be. ISA leve... | 05/08/2007 |
| 7213136 | Apparatus and method for redundant zero micro-operation removal A method and apparatus for redundant zero micro-operation removal. In one embodiment, the method includes the identification of a predetermined macro-instruction. Once identified, a value associated with a source register operand of the identified macro-instruction ... | 05/01/2007 |
| 7210030 | Programmable memory initialization system and method The present invention provides for a system for programmable memory initialization. A configuration module is configured with initialization control commands and associated configuration information. An initialization module is coupled to the configuration module an... | 04/24/2007 |
| 7206925 | Backing Register File for processors A processor is defined by a new architectural feature called a Backing Register File, where a Backing Register File is a set of randomly accessible registers capable of holding values, and further are directly connected to the processor's register files. The process... | 04/17/2007 |
| 7191314 | Reconfigurable CPU with second FSM control unit executing modifiable instructions A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set associated therewith. Associated with the second control unit is at least one... | 03/13/2007 |
| 7185183 | Atomic update of CPO state A group of bit set and bit clear instructions are provided for a microprocessor to allow atomic modification of privileged architecture control registers. The bit set and bit clear instructions include an opcode that designates to the microprocessor that the instruc... | 02/27/2007 |
| 7162612 | Mechanism in a microprocessor for executing native instructions directly from memory An microprocessor apparatus and method are provided for executing native instructions directly from memory. The apparatus includes instruction translation logic and bypass logic. The instruction translation logic retrieves macro instructions provided via an external... | 01/09/2007 |
| 7162621 | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one pa... | 01/09/2007 |
| 7139898 | Fetch and dispatch disassociation apparatus for multistreaming processors A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one ... | 11/21/2006 |
| 7134005 | Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte A microprocessor caches in a branch target address cache (BTAC), for each of a plurality of previously executed branch instructions: a prediction of whether the branch instruction will be taken and is present in a cache line of instruction bytes provided by an instr... | 11/07/2006 |
| 7131125 | Method and system for sharing a computer resource between instruction threads of a multi-threaded process Route switch packet architecture processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architectu... | 10/31/2006 |
| 7124280 | Execution control apparatus of data driven information processor for instruction inputs An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that stores N (N≧2) waiting data and respective data valid flags in one addr... | 10/17/2006 |
| 7120789 | System and method for portable on-demand central processing unit A method and a system for providing a processor to a computer system through a removable CPU module. The processor on the removable CPU module may be shared by multiple computer systems by inserting the module into different computer systems at different times. Upon... | 10/10/2006 |
| 7111151 | Microprocessor including microcode unit that only changes the value of control signals required for the current cycle operation for reduced power consumption and method therefor A microprocessor, method and signal-bearing medium for storing a program for executing the method, includes a microcode unit for outputting control signals, for each of a plurality of instructions, required by the microprocessor for executing the instructions. The m... | 09/19/2006 |
| 7103758 | Microcontroller performing safe recovery from standby mode A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is halted. The standby mode is exited by input of an interrupt. The microcont... | 09/05/2006 |
| 7103759 | Microcontroller architecture supporting microcode-implemented peripheral devices Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for storing microcode instructions; execution circuitry operable to execute... | 09/05/2006 |
| 7092125 | Method of printing using PC and printer It is necessary that paper be moved past the printhead at a constant velocity to obtain artifact-free printing. Therefore the printhead requires a constant stream of data during printing. Whilst it is possible to rasterize the page using a page description language ... | 08/15/2006 |
| 7072076 | Printing method using PC rendering It is necessary that paper be moved past the printhead at a constant velocity to obtain artifact—free printing. Therefore the printhead requires a constant stream of data during printing. Whilst it is possible to rasterize the page using a page description languag... | 07/04/2006 |
