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| Number | Title | Issue Date |
| 8176301 | Millicode assist instructions for millicode store access exception checking Millicode store access checking instructions are provided via an operand access control register (OACR) including a test modifier indicator, which is communicatively coupled to an instruction unit subsystem, the instruction unit subsystem for fetching and decoding i... | 05/08/2012 |
| 8099587 | Compressing and accessing a microcode ROM An arrangement is provided for compressing microcode ROM (“uROM”) in a processor and for efficiently accessing a compressed “uROM”. A clustering-based approach may be used to effectively compress a uROM. The approach groups similar columns of microcode into ... | 01/17/2012 |
| 8082430 | Representing a plurality of instructions with a fewer number of micro-operations A micro-operation (uop) fusion technique. More particularly, embodiments of the invention relate to a technique to fuse two or more uops originating from two or more instructions. ... | 12/20/2011 |
| 8074061 | Executing micro-code instruction with delay field and address of next instruction which is decoded after indicated delay A microsequencer is disclosed that controls the order in which microcode instructions are fetched from a microcode ROM. Each microcode instruction includes an execution command for execution by one or more execution units. Each microcode instruction also includes a ... | 12/06/2011 |
| 8069340 | Microprocessor with microarchitecture for efficiently executing read/modify/write memory operand instructions A microprocessor instruction translator translates a macroinstruction into three microinstructions to perform a read/modify/write operation on a memory operand. A first microinstruction instructs the microprocessor to calculate a source address and to load the memor... | 11/29/2011 |
| 8001365 | Exchange of processing metric information between nodes Method and nodes are provided for propagating between the nodes information about processing capacity of peer nodes. Two types of signals are sent from propagating nodes towards their peer nodes. A propagating node sends first signal type at a constant rate and a se... | 08/16/2011 |
| 7991986 | Microprocessor starting to execute a computer program at a predetermined interval A microprocessor which is adapted to start a second task at a predetermined time when a first task is running if a current time becomes to be equal to the predetermined time is disclosed. The microprocessor executing an instruction read out from a program address up... | 08/02/2011 |
| 7831819 | Filter micro-coded accelerator Method and apparatus for a filter micro-code accelerator are described. ... | 11/09/2010 |
| 7725698 | Operation apparatus having sequencer controlling states of plurality of operation units and operation apparatus control method therefor An operation apparatus includes a plurality of operation device units; a configuration memory storing setting information provided for each predetermined state of the plurality of operation device units; and a sequencer controlling the plurality of operation device ... | 05/25/2010 |
| 7610476 | Multiple control sequences per row of microcode ROM Various embodiments of methods and systems for storing multiple groups of microcode operations and corresponding control sequences per row of microcode ROM are disclosed. In one embodiment, an integrated circuit may include a microcode ROM coupled to a control seque... | 10/27/2009 |
| 7526638 | Hardware alteration of instructions in a microcode routine Processor logic gates are used to modify microcode instructions, while they are being executed. The results of previous operations are used by the hardware to modify subsequent instructions in a microcode routine. This gives the effect of branching and also reduces ... | 04/28/2009 |
| 7519799 | Apparatus having a micro-instruction queue, a micro-instruction pointer programmable logic array and a micro-operation read only memory and method for use thereof Embodiments of the present invention relate to high-performance processors, and more specifically, to processors that store all operation information associated with each instruction in a single memory. A processor including multiple programmable logic arrays (PLAs)... | 04/14/2009 |
| 7490230 | Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetc... | 02/10/2009 |
| 7441111 | Controlled program execution by a portable data carrier In a method for controlled program execution by a portable data carrier, the value of a status counter (ZZ) is altered during execution of each controlled section (36.x) of an executed program (30) in order to reflect the processing of the respective c... | 10/21/2008 |
| 7441103 | High-performance, superscalar-based computer system with out-of-order instruction execution A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program orde... | 10/21/2008 |
| 7437537 | Methods and apparatus for predicting unaligned memory access In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The add... | 10/14/2008 |
| 7415602 | Apparatus and method for processing a sequence of jump instructions An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining t... | 08/19/2008 |
| 7412590 | Information processing apparatus and context switching method An information processing apparatus which, when executing a plurality of predetermined units of processing, executes the predetermined units of processing in parallel by a processor by switching between contexts associated with the respective predetermined units. Th... | 08/12/2008 |
| 7404068 | Single operation per-bit memory access Mechanisms for performing per-bit operations in system memory in a single operation thereby obviating the need for semaphore mechanisms when performing per-bit operations. A processor accesses an instruction that identifies the specific bit of system memory that is ... | 07/22/2008 |
| 7401328 | Software-implemented grouping techniques for use in a superscalar data processing system A data processing system includes a grouping tool coupled to a processor. The grouping tool groups the stream of instructions such that each group of instructions has a dimensionless signature annotated thereto. An instruction prefetch unit of the processor fetches ... | 07/15/2008 |
| 7401211 | Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor In a multi-threaded processor, a long latency data dependent thread is flushed from the execution pipelines. Once the stalled thread is flushed, the non-stalling threads in the pipeline can continue their execution. Several resources are used to reduce this unwanted... | 07/15/2008 |
| 7398376 | Instructions for ordering execution in pipelined processes Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory write operations local to a CPU to occur in an arbitrary order, and plac... | 07/08/2008 |
| 7389407 | Central control system and method for using state information to model inflight pipelined instructions A method and apparatus to control logic sections of a pipeline instruction processor is disclosed. A state machine is provided that models the flow of instructions through the pipeline. The state machine is capable of modeling execution for all combinations of instr... | 06/17/2008 |
| 7386710 | Methods and apparatus for scalable array processor interrupt detection and response Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable ... | 06/10/2008 |
| 7376818 | Program translator and processor Multiple instructions, specifying equivalent operations but designating different execution units, are stored beforehand on an instruction exchange table. First, a primary compiler compiles a source program into a set of machine-readable instructions. From the set o... | 05/20/2008 |
| 7376844 | Countermeasure method for a microcontroller based on a pipeline architecture A countermeasure method for a microcontroller that executes sequences of instructions. The instructions are executed according to a pipeline method. At least one waiting time is randomly introduced between two consecutive instructions and/or within at least one inst... | 05/20/2008 |
| 7373225 | Method and system for optimizing vehicle diagnostic trees using similar templates A method and system for optimizing vehicle diagnostic trees using similar templates is provided. Diagnostic trees may be modified to include diagnostic code tips or further suggestions or instructions indicating what tool to use or how to use the tool. The diagnosti... | 05/13/2008 |
| 7373226 | System and method for optimizing vehicle diagnostic tress using similar templates A system and method for evaluating and applying edits from one diagnostic tree to another matching or similar diagnostic tree is described. The system includes a diagnostic tree editor, a library, and a comparison engine. These elements work together to convert an O... | 05/13/2008 |
| 7373490 | Emptying packed data state during execution of packed data instructions A method in a computer system, one embodiment includes accessing a packed data instruction and generating a corresponding set of control bits to cause a processor to alter a top of stack to zero of a programmer visible register file, accessing a floating point instr... | 05/13/2008 |
| 7370136 | Efficient and flexible sequencing of data processing units extending VLIW architecture A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycl... | 05/06/2008 |
| 7370181 | Single stepping a virtual machine guest using a reorder buffer Embodiments of apparatuses, systems, and methods for single stepping a virtual machine guest using a reorder buffer are disclosed. In one embodiment, an apparatus includes a sequencer and a reorder buffer. The sequencer is to issue micro-operations. The reorder buff... | 05/06/2008 |
| 7369450 | Nonvolatile memory having latching sense amplifier and method of operation A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharg... | 05/06/2008 |
| 7360062 | Method and apparatus for selecting an instruction thread for processing in a multi-thread processor The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave r... | 04/15/2008 |
| 7353337 | Reducing cache effects of certain code pieces Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since the instructions contained in the instruction cache prior to execution ... | 04/01/2008 |
| 7353505 | Tracing the execution path of a computer program The invention relates to tracing the execution path of a computer program comprising at least one module including a plurality of instructions. At least one of these instructions is a branch instruction. Each branch instruction is identified and evaluated to be one ... | 04/01/2008 |
| 7349398 | Method and apparatus for out-of-order processing of packets A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different ones of a plurality of reorder contexts. The method also includes, for... | 03/25/2008 |
| 7349399 | Method and apparatus for out-of-order processing of packets using linked lists These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing of packets using linked lists is described. In one embodiment, the m... | 03/25/2008 |
| 7343602 | Software controlled pre-execution in a multithreaded processor A processor capable of running multiple threads runs a program in one thread (called the “main” thread) and at least a portion of the same program in another thread (called the “pre-execution” thread). The program in the main thread includes instructions tha... | 03/11/2008 |
| 7340643 | Replay mechanism for correcting soft errors A processor is provided that implements a replay mechanism to recover from soft errors. The processor includes a protected execution unit, a check unit to detect errors in results generated by the protected execution unit, and a replay unit to track selected instruc... | 03/04/2008 |
| 7330963 | Resolving all previous potentially excepting architectural operations before issuing store architectural operation Embodiments include various methods, apparatuses, and systems in which a processor includes an out of order issue engine and an in-order execution pipeline. For some embodiments, the issue engine may be remote from the execution pipeline and execution resources may ... | 02/12/2008 |
