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| Number | Title | Issue Date |
| 8127120 | Secured processing unit A method for executing by a processing unit a program stored in a memory, includes: detecting a piece of information during the execution of the program by the processing unit, and if the information is detected, triggering the execution of a hidden subprogram by th... | 02/28/2012 |
| 7444501 | Methods and apparatus for recognizing a subroutine call An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a non-sequential change in program flow, and a third input for receiving the nex... | 10/28/2008 |
| 7412593 | Processor for processing a program with commands including a mother program and a sub-program A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump command. The processor has a command processor, which is adapted in the mot... | 08/12/2008 |
| 7398372 | Fusing load and alu operations Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops ... | 07/08/2008 |
| 7392370 | Method and apparatus for autonomically initiating measurement of secondary metrics based on hardware counter values for primary metrics A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each ... | 06/24/2008 |
| 7383425 | Massively reduced instruction set processor This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video... | 06/03/2008 |
| 7350062 | Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to proce... | 03/25/2008 |
| 7305543 | Memory organization allowing single cycle pointer addressing where the address of the pointer is also contained in one of the memory locations All pointer-based accesses require first that the value contained in a pointer register to be read and then that value be used as an address to the appropriate region in random access memory (RAM). As implemented today, this requires two memory read access cycles, e... | 12/04/2007 |
| 7237093 | Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams In a multi-streaming processor having a memory cache, a system for fetching instructions from individual ones of multiple streams to an instruction pipeline is provided, comprising a fetch algorithm for selecting from which stream to fetch an instruction, and a hit/... | 06/26/2007 |
| 7237098 | Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address. Typically the return stack is more accurate. However, if the return stack... | 06/26/2007 |
| 7231511 | Microinstruction pointer stack including speculative pointers for out-of-order execution Methods and apparatus, including computer program products, for a microinstruction pointer stack in a processor. A method executed in a processor includes executing microcode (μcode) addressed by pointers stored in an out-of-order microinstruction pointer (μIP) st... | 06/12/2007 |
| 7219218 | Vector technique for addressing helper instruction groups associated with complex instructions The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calcu... | 05/15/2007 |
| 7203825 | Sharing information to reduce redundancy in hybrid branch prediction A hybrid branch predictor is disclosed. The predictor includes prediction aiding information, a plurality of branch predictors to provide a plurality of branch predictions, a plurality of storage elements to hold less than full extent of the branch predictions, but ... | 04/10/2007 |
| 7203826 | Method and apparatus for managing a return stack A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of retu... | 04/10/2007 |
| 7200740 | Apparatus and method for speculatively performing a return instruction in a microprocessor A branch prediction apparatus that employs dual call/return stacks to predict return addresses in a microprocessor. The apparatus includes a first call/return stack that provides a speculative return address based upon a return instruction hit in a speculative branc... | 04/03/2007 |
| 7181576 | Method for synchronizing a cache memory with a main memory Method for synchronizing a cache memory with a main memory, the cache memory provided to buffer-store data between a processor and the main memory, and memory entries of the cache memory each having a data area and an identification area. The processor provides a sy... | 02/20/2007 |
| 7162621 | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at least one virtual instruction that includes an index and at least one pa... | 01/09/2007 |
| 7134005 | Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte A microprocessor caches in a branch target address cache (BTAC), for each of a plurality of previously executed branch instructions: a prediction of whether the branch instruction will be taken and is present in a cache line of instruction bytes provided by an instr... | 11/07/2006 |
| 7127718 | Multitasking microcontroller for controlling the physical layer of a network interface card and method of operation There is disclosed an apparatus for controlling a physical layer interface of a network interface card in real time. The apparatus comprises: 1) a first memory for storing a multitasking control program, the multitasking control program comprising a main routine and... | 10/24/2006 |
| 7124281 | Processing system having sequential address indicator signals Embodiments of the present inventions relate to processors having sequential address indicator signals, also referred to as sequence signals, for indicating when accessed addresses are sequential. One embodiment relates to a processing system for accessing memory ha... | 10/17/2006 |
| 7069424 | Placing front instruction in replay loop to front to place side instruction into execution stream upon determination of criticality A method and apparatus for whacking a μOP based upon the criticality of that μOP. Also disclosed are embodiments of a method for determining the criticality of a μOP. ... | 06/27/2006 |
| 7055022 | Paired load-branch operation for indirect near jumps A microprocessor apparatus is provided for performing an indirect near jump operation that includes paired operation translation logic, load logic, and execution logic. The paired operation translation logic receives an indirect near jump macro instruction, and gene... | 05/30/2006 |
| 7039793 | Microprocessor apparatus and method for accelerating execution of repeat string instructions A method and apparatus are provided for processing repeat string instructions with increased efficiency in a processor pipeline. Rather than explicitly generating an initial count register setup micro instruction each time a repeat (REP) prefix in encountered, the p... | 05/02/2006 |
| 7035999 | Register window fill technique for retirement window having entry size less than amount of fill instructions A register window fill technique for a retirement window having an entry size less than a number of fill instructions used in a fill condition is provided. The technique uses modified fill instructions that allow the retirement window to retire a portion of the fill... | 04/25/2006 |
| 7024541 | Register window spill technique for retirement window having entry size less than amount of spill instructions A register window spill technique for an retirement window having an entry size less than a number of spill instructions used in a spill condition is provided. The technique uses modified spill instructions that allow the retirement window to retire a portion of the... | 04/04/2006 |
| 6958625 | Programmable logic device with hardwired microsequencer A programmable logic device configurable to implement a finite state machine includes a hardwired microsequencer for executing microinstructions to sequence the finite state machine. The hardwired microsequencer includes a sequence memory for storing the microinstru... | 10/25/2005 |
| 6957319 | Integrated circuit with multiple microcode ROMs Integrated circuits having multiple independently accessible microcode ROMs. An integrated circuit may include a microcode unit and a plurality of microcode ROMs fabricated within the same integrated circuit. The microcode unit may be configured to receive a microco... | 10/18/2005 |
| 6957322 | Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion A microcode instruction unit for a processor may include a microcode memory having entries for storing microcode instructions. A decoder for the microcode memory may decode microcode addresses to select entries of the microcode memory. A microcode entry point genera... | 10/18/2005 |
| 6954849 | Method and system to use and maintain a return buffer An instruction pipeline in a microprocessor includes one or more of the pipelines maintaining a return buffer. Upon detecting a call instruction, a pipeline will push the return address onto its return buffer. The pipeline will then determine if the call instruction... | 10/11/2005 |
| 6922773 | System and method for encoding constant operands in a wide issue processor For use in a data processor comprising an instruction execution pipeline comprising N processing stages, a system and method of encoding constant operands is disclosed. The system comprises a constant generator unit that is capable of generating both short constant ... | 07/26/2005 |
| 6910119 | Instruction pipe and stall therefor to accommodate shared access to return stack buffer In a system where multiple instruction pipes share access to a common return stack buffer (RSB), coordination is provided to ensure that no instruction pipe gains unfair access to the RSB. Additionally, further coordination control may be provided to ensure that a p... | 06/21/2005 |
| 6910124 | Apparatus and method for recovering a link stack from mis-speculation A method of performing link stack operations comprises the steps of reading and writing to a link stack. During a write, a location in the link stack pointed to by a current write pointer is selected and a link address associated with an instruction and a current re... | 06/21/2005 |
| 6907511 | Reducing transitions on address buses using instruction-set-aware system and method An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method retrieves an instruction from a memory location indicated by the first ... | 06/14/2005 |
| 6898699 | Return address stack including speculative return address buffer with back pointers An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative return address buffer and a committed return address buffer, both of whic... | 05/24/2005 |
| 6865669 | Methods for optimizing memory resources during initialization routines of a computer system Methods for optimizing of memory resources during an initialization routine of a computer system which prepares the computer system for loading of an operating system is disclosed. One exemplary method includes receiving a request from a system BIOS to locate an amo... | 03/08/2005 |
| 6857063 | Data processor and method of operation A data processor executes an instruction (JAVASW) to implement efficient interpreter functionality by combining the tasks of table jumps and thread or task switching which is controlled by a running value such as a counter or a timer. Execution of the instruction al... | 02/15/2005 |
| 6842842 | Method and system to preprogram and predict a next microcode address A microprocessor includes a first memory to store microcode and a second memory to store predicted micro-operation addresses. Micro-operation addresses are predicted, stored in memory, and retrieved to get the next micro-operations from the microcode memory. Mispred... | 01/11/2005 |
| 6807626 | Execution of a computer program A computer system has a memory which holds a computer program consisting of a sequence of program instructions. The format of the program instructions depends on an instruction mode of the computer system. A decoder is arranged to receive and decode program instruct... | 10/19/2004 |
| 6718414 | Function modification in a write-protected operating system An apparatus and method are disclosed for runtime modification of called functions within a write-protected operating system. The access state of a processor is altered to allow modification of the function code, and a redirection to a hook function is inserted at a... | 04/06/2004 |
| 6697938 | Microcomputer executing an ordinary branch instruction and a special branch instruction A microcomputer has a built-in memory and is accessible to an external memory. The microcomputer executes a specific area branch instruction "JM" as an executable instruction. The specific area branch instruction "JM" is a branch instruction restricted to... | 02/24/2004 |
