Did You Know...
...that a workman who left the soap mixing machine on too long was responsible for making Ivory Soap? He was so embarrassed by his mistake that he threw the mess in a stream. Imagine his dismay when the evidence of his error floated to the surface! Result: Ivory soap, the soap that floats.
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| Number | Title | Issue Date |
| 8055886 | Processor micro-architecture for compute, save or restore multiple registers and responsive to first instruction for repeated issue of second instruction An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of said b... | 11/08/2011 |
| 8019982 | Loop data processing system and method for dividing a loop into phases A data processing system and method. The data processing system includes a processor core that executes a program; a loop accelerator that has an array consisting of a plurality of data processing cells and executes a loop in a program by configuring the array accor... | 09/13/2011 |
| 8019981 | Loop instruction execution using a register identifier Methods and apparatus are provided for performing loop execution. Modifier registers are used to hold loop counter values. Modifier register information and program memory address information are included in the loop instruction. When a processor executes a loop ins... | 09/13/2011 |
| 7996661 | Loop processing counter with automatic start time set or trigger modes in context reconfigurable PE array A dynamic reconfigurable circuit that implements optional processing by dynamically switching a processing content of a reconfigurable processing element (PE) and a connection content between the PEs in accordance with a context, includes: a configuration register s... | 08/09/2011 |
| 7991985 | System and method for implementing and utilizing a zero overhead loop Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism, and modification of parameters at runtime, with the breakpoint mechani... | 08/02/2011 |
| 7991984 | System and method for executing loops in a processor A loop control system comprises at least one loop flag in an instruction word, at least one loop counter associated with the at least one loop flag operable to store and compute a number of times a program loop is to be executed, at least one start address register ... | 08/02/2011 |
| 7987347 | System and method for implementing a zero overhead loop Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism which is additionally used in debugging in order to provide some of the... | 07/26/2011 |
| 7975134 | Macroscalar processor architecture A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive o... | 07/05/2011 |
| 7945768 | Method and apparatus for nested instruction looping using implicit predicates A method and apparatus for executing a nested program loop on a vector processor, the loop comprising outer-pre, inner and outer-post portions. An input stream unit of the vector processor provides a data value to a data path and sets an associated data validity tag... | 05/17/2011 |
| 7937574 | Precise counter hardware for microcode loops In an embodiment, a microcode unit for a processor is contemplated. The microcode unit comprises a microcode memory storing a plurality of microcode routines executable by the processor, wherein each microcode routine comprises two or more microcode operations. Coup... | 05/03/2011 |
| 7917739 | Storage medium storing calculation processing visualization program, calculation processing visualization apparatus, and calculation processing visualization method The execution status of pipeline processing is highly visualized by appropriately displaying processes forming loops in a simplified manner. A loop-information storage unit stores loop-defining information specifying the address of an instruction that causes a pipel... | 03/29/2011 |
| 7913069 | Processor and method for executing a program loop within an instruction word A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. Instruction words (48)... | 03/22/2011 |
| 7886134 | Loop iteration prediction by supplying pseudo branch instruction for execution at first iteration and storing history information in branch prediction unit This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a block repeat, the loop control unit branches to the first instruction in the loop and sends a pseudo branch... | 02/08/2011 |
| 7873820 | Processor utilizing a loop buffer to reduce power consumption The present invention provides processing systems, apparatuses, and methods that reduce power consumption with the use of a loop buffer. In an embodiment, an instruction fetch unit of a processor initially provides instructions from an instruction cache to an execut... | 01/18/2011 |
| 7836289 | Branch predictor for setting predicate flag to skip predicated branch instruction execution in last iteration of loop processing A program execution control device which controls execution of a program by a processor having a predicate function for conditional execution of an instruction, wherein the program includes a branch instruction to control iterations in loop processing, the branch in... | 11/16/2010 |
| 7725696 | Method and apparatus for modulo scheduled loop execution in a processor architecture A processor method and apparatus that allows for the overlapped execution of multiple iterations of a loop while allowing the compiler to include only a single copy of the loop body in the code while automatically managing which iterations are active. Since the prol... | 05/25/2010 |
| 7685411 | Multi-mode instruction memory unit An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution... | 03/23/2010 |
| 7669042 | Pipeline controller for context-based operation reconfigurable instruction set processor An instruction execution pipeline for use in a data processor. The instruction execution pipeline comprises: 1) an instruction fetch stage; 2) a decode stage; 3) an execution stage; and 4) a write-back stage. The instruction pipeline repetitively executes a loop of ... | 02/23/2010 |
| 7590831 | Loop accelerator and data processing system having the same Provided are a loop accelerator and a data processing system having the loop accelerator. The data processing system includes a loop accelerator which executes a loop part of a program, a processor core which processes a remaining part of the program except the loop... | 09/15/2009 |
| 7571305 | Reusing a buffer memory as a microcache for program instructions of a detected program loop A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon... | 08/04/2009 |
| 7558948 | Method for providing zero overhead looping using carry chain masking A method for reducing overhead on a loop of a plurality of instructions is disclosed. The method includes providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value fo... | 07/07/2009 |
| 7529917 | Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while execu... | 05/05/2009 |
| 7526637 | Adaptive execution method for multithreaded processor-based parallel system Provided is a parallel program execution method in which in order to reflect structural characteristics of a multithreaded processor-based parallel system, performance of the parallel loop is predicted while compiling or executing using a performance prediction mode... | 04/28/2009 |
| 7478227 | Apparatus and method for optimizing loop buffer in reconfigurable processor A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one ... | 01/13/2009 |
| 7475231 | Loop detection and capture in the instruction queue A system and a method to identify a conditional branch instruction having a program counter and a target address, and increment a loop count each time the program counter and the target address equal a stored program counter and a target address. The system and meth... | 01/06/2009 |
| 7447886 | System for expanded instruction encoding and method thereof A system and methods are discussed for providing additional capabilities to some instructions associated with loop execution. A standard set of instructions is processed using only a standard instruction size. Some loop instructions are processed with a standard ins... | 11/04/2008 |
| 7447887 | Multithread processor To guarantee response time while strictly maintaining the priority specified by software, a processor (1) which is a multithread processor having a thread multiplexer (10), and an issue information buffer (ISINF). An instruction code, and issue informa... | 11/04/2008 |
| 7437719 | Combinational approach for developing building blocks of DSP compiler An approach that uses a combinatorial approach by adopting natural language processing with the application of Finite State Morphology (FSM) to transform source code into an efficient assembly code. In one example embodiment, this is accomplished by modifying a sour... | 10/14/2008 |
| 7437544 | Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an instruction store for storing the sequence of instructions, and a processin... | 10/14/2008 |
| 7434031 | Execution displacement read-write alias prediction RAW aliasing can be predicted with register bypassing based at least in part on execution displacement alias prediction. Repeated aliasing between read and write operations (e.g., within a loop), can be reliably predicted based on displacement between the aliasing o... | 10/07/2008 |
| 7428632 | Branch prediction mechanism using a branch cache memory and an extended pattern cache A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a plurality of compressed representations of these such that when they ... | 09/23/2008 |
| 7406590 | Methods and apparatus for early loop bottom detection in digital signal processors Methods and apparatus are provided for processing variable width instructions in a pipelined processor. The apparatus includes an instruction decoder configured to decode a loop setup instruction, having a loop setup instruction address, to obtain a loop bottom offs... | 07/29/2008 |
| 7401205 | High performance RISC instruction set digital signal processor having circular buffer and looping controls A DSP superscalar architecture employing dual multiply accumulate pipelines. Dual MAC pipelines allow for a seem less transition between established RISC instruction sets and extended DSP instructions sets. Relocatable opcodes are provide to allow further extensions... | 07/15/2008 |
| 7395419 | Macroscalar processor architecture A macroscalar processor architecture is described herein. In one embodiment, an exemplary processor includes one or more execution units to execute instructions and one or more iteration units coupled to the execution units. The one or more iteration units receive o... | 07/01/2008 |
| 7395531 | Framework for efficient code generation using loop peeling for SIMD loop code with multiple misaligned statements A system and method is provided for vectorizing misaligned references in compiled code for SIMD architectures that support only aligned loads and stores. In this framework, a loop is first simdized as if the memory unit imposes no alignment constraints. The compiler... | 07/01/2008 |
| 7380112 | Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”... | 05/27/2008 |
| 7370136 | Efficient and flexible sequencing of data processing units extending VLIW architecture A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycl... | 05/06/2008 |
| 7366885 | Method for optimizing loop control of microcoded instructions A method for optimizing loop control of microcoded instructions includes identifying an instruction as a repetitive microcode instruction such as a move string instruction, for example, having a repeat prefix. The repetitive microcode instruction may include a loop ... | 04/29/2008 |
| 7363467 | Dependence-chain processing using trace descriptors having dependency descriptors An apparatus and method for a processor microarchitecture that quickly and efficiently takes large steps through program segments without fetching all intervening instructions. The microarchitecture processes descriptors of trace sequences in program order so as to ... | 04/22/2008 |
| 7356806 | Method and system for processing records of events during use of a communications system In a communications network that provides services to a plurality of users, events occurring during service processing are accumulated in an event record and sent to a record processor to perform post-processing, such as assessing charges to be billed to users of th... | 04/08/2008 |
