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| Number | Title | Issue Date |
| 8117423 | Pipeline replay support for multicycle operations Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15) of the processor. The control information pipeline is sy... | 02/14/2012 |
| 8095775 | Instruction pointers in very long instruction words During operation of a VLIW processor, a very long instruction word is fetched. A portion of the very long instruction word that includes a pointer to an instruction is identified, and the instruction pointed to by the pointer is retrieved from a location of an instr... | 01/10/2012 |
| 8019971 | Processor for executing highly efficient VLIW A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicat... | 09/13/2011 |
| 8015391 | Simultaneous multiple thread processor increasing number of instructions issued for thread detected to be processing loop A processor simultaneously issues instructions to multiple threads in a same instruction execution cycle. An instruction issuer controls issuance of an instruction for each of the multiple threads. A detector detects, for each of the multiple threads, whether a loop... | 09/06/2011 |
| 7962719 | Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations... | 06/14/2011 |
| 7861061 | Processor instruction including option bits encoding which instructions of an instruction packet to execute A processor and a method for executing VLIW instructions by first fetching a VLIW instruction and then identifying from option bits encoded in a first one of the instructions within the fetched VLIW instruction packet which, if any, of the remaining instructions wit... | 12/28/2010 |
| RE41703 | Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A maski... | 09/14/2010 |
| 7774581 | Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same An apparatus and a method are provided for a parallel processing very long instruction word (VLIW) computer. The apparatus includes: an index code generation unit sequentially generating an index code, which is associated with a number of no operation (NOP) instruct... | 08/10/2010 |
| 7685403 | Pipeline replay support for multi-cycle operations Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15) of the processor. The control information pipeline is sy... | 03/23/2010 |
| 7664929 | Data processing apparatus with parallel operating functional units A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each instruction word in parallel. The instructions from each of at least ... | 02/16/2010 |
| 7647474 | Saving system context in the event of power loss Embodiments of a method and system for saving system context after a power outage are disclosed herein. A power agent operates to reduce the possibility of data corruption due to partially written data during an unexpected power outage. The power agent can determine... | 01/12/2010 |
| 7647473 | Instruction processing method for verifying basic instruction arrangement in VLIW instruction for variable length VLIW processor An instruction processing method for checking an arrangement of basic instructions in a very long instruction word (VLIW) instruction, suitable for language processing systems, an assembler and a compiler, used for processors which execute variable length VLIW instr... | 01/12/2010 |
| 7574583 | Processing apparatus including dedicated issue slot for loading immediate value, and processing method therefor Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small immediate values. The present invention describes a processing apparatus, ... | 08/11/2009 |
| 7533244 | Network-on-chip dataflow architecture Network-on-Chip Dataflow Architecture is the new microprocessor architecture. It consists of many processing elements connecting together via two distinct networks namely instruction network and data network. Instructions are fetched into the processing elements thr... | 05/12/2009 |
| 7533243 | Processor for executing highly efficient VLIW A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicat... | 05/12/2009 |
| 7506137 | Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing framework are described. In one aspect, an initiation mechanism also ac... | 03/17/2009 |
| 7484075 | Method and apparatus for providing fast remote register access in a clustered VLIW processor using partitioned register files Effective remote register file access time can be reduced in a clustered VLIW processor using partitioned register files and some additional hardware for pre-fetching remote registers. An instruction pre-fetcher and an instruction pre-decoder is used for pre-fetchin... | 01/27/2009 |
| 7444276 | Hardware acceleration system for logic simulation using shift register as local cache A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect system that communicatively couples the processor units to each other. E... | 10/28/2008 |
| 7437534 | Local and global register partitioning technique A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each of the register file segments being associated to one of the pluralit... | 10/14/2008 |
| 7424594 | Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations... | 09/09/2008 |
| 7418575 | Long instruction word processing with instruction extensions A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of computational instructions and long instruction word instructions with ... | 08/26/2008 |
| 7412591 | Apparatus and method for switchable conditional execution in a VLIW processor An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and decodes instructions from a fetch unit for decoding and sending the dec... | 08/12/2008 |
| 7409530 | Method and apparatus for compressing VLIW instruction and sharing subinstructions A VLIW instruction format is introduced having a set of control bits which identify subinstruction sharing conditions. At compilation the VLIW instruction is analyzed to identify subinstruction sharing opportunities. Such opportunities are encoded in the control bit... | 08/05/2008 |
| 7401204 | Parallel Processor efficiently executing variable instruction word A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units pe... | 07/15/2008 |
| 7398372 | Fusing load and alu operations Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops ... | 07/08/2008 |
| 7395408 | Parallel execution processor and instruction assigning making use of group number in processing elements The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data... | 07/01/2008 |
| 7383422 | Very long instruction word (VLIW) computer having an efficient instruction code format A Very Long Instruction Word (VLIW) processor having an instruction set with a reduced size resulting in a small number of bits being necessary to specify registers. The VLIW processor includes a register file, and first through third operation units, and executes a... | 06/03/2008 |
| 7380100 | Data processing system and control method utilizing a plurality of date transfer means The present invention provides a data processing system that includes a plurality of processing units and first, second, and third data transfer means. The first data transfer means connects a plurality of processing units in a network, exchanges first data, and con... | 05/27/2008 |
| 7376812 | Vector co-processor for configurable and extensible processor architecture A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maint... | 05/20/2008 |
| 7376813 | Register move instruction for section select of source operand A data processing apparatus execution unit includes a multiplexer having inputs receiving data from sections of a source data register or registers. The multiplexer selects data from one section to store in a destination data register. The execution unit may zero ex... | 05/20/2008 |
| 7373121 | Apparatus and method for processing a deterministic data flow associated with a wireless communication signal The invention is directed to an apparatus, method and system for providing reduced power consumption, fast processing of digitized communication signals and relatively easy reconfiguration for different applications, such as communication protocols/standards. The in... | 05/13/2008 |
| 7370182 | Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing un... | 05/06/2008 |
| 7370136 | Efficient and flexible sequencing of data processing units extending VLIW architecture A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each instruction may include an iteration count specifying the number of cycl... | 05/06/2008 |
| 7366032 | Multi-ported register cell with randomly accessible history A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality... | 04/29/2008 |
| 7366877 | Speculative instruction issue in a simultaneously multithreaded processor A method for optimizing throughput in a microprocessor that is capable of processing multiple threads of instructions simultaneously. Instruction issue logic is provided between the input buffers and the pipeline of the microprocessor. The instruction issue logic sp... | 04/29/2008 |
| 7366987 | Interrupt processing in display control The present invention provides a display control system suitable to flexible and smooth presentation. The invention can include a projector that stores page data included in projector display data in a stack area by a stack system in which the page data correspondin... | 04/29/2008 |
| 7366876 | Efficient emulation instruction dispatch based on instruction width In one embodiment, a state machine receives a plurality of instructions from an instruction register to be processed by a digital signal processor. After receiving a single RTI, the state machine loads each of the plurality of instructions one at time and determines... | 04/29/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7366874 | Apparatus and method for dispatching very long instruction word having variable length Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding u... | 04/29/2008 |
| 7366932 | Method and apparatus to adapt the clock rate of a programmable coprocessor for optimal performance and power dissipation A coprocessor executing one among a set of candidate kernel loops within an application operates at the minimal clock frequency satisfying schedule constraints imposed by the compiler and data bandwidth constraints. The optimal clock frequency is statically determin... | 04/29/2008 |
