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| Number | Title | Issue Date |
| 8171269 | Branch target buffer with entry source field for use in determining replacement priority Various embodiments of the present invention provide systems and methods for branch prediction. As an example, some embodiments of the present invention provides processor circuits that include a program address circuit, a branch target buffer, a branch prediction r... | 05/01/2012 |
| 8090934 | Systems and methods for providing security for computer systems Hardware and/or software countermeasures are provided to reduce or eliminate vulnerabilities due to the observable and/or predictable states and state transitions of microprocessor components such as instruction cache, data cache, branch prediction unit(s), branch t... | 01/03/2012 |
| 8019980 | Branch target buffer system and method for storing target address A branch target buffer (BTB) system and method for storing target address is provided. The BTB system is applicable to a 16-bit, 32-bit, 64-bit or higher processor architecture. When the target address of the branch instruction is stored, the BTB stores the variatio... | 09/13/2011 |
| 7941653 | Jump instruction having a reference to a pointer for accessing a branch address table Methods and apparatus are provided for performing a jump operation in a pipelined digital processor. The method includes writing target addresses of jump instructions to be executed to a memory table, detecting a first jump instruction being executed by the processo... | 05/10/2011 |
| 7937573 | Metric for selective branch target buffer (BTB) allocation A method and data processing system allocates entries in a branch target buffer (BTB). Instructions are fetched from a plurality of instructions and one of the plurality of instructions is determined to be a branch instruction. A corresponding branch target address ... | 05/03/2011 |
| 7873818 | System and method for search area confined branch prediction A system and method for performing search area confined branch prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information for branch prediction, where the branch information includes a branch address. The syst... | 01/18/2011 |
| 7836287 | Reducing the fetch time of target instructions of a predicted taken branch instruction A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instru... | 11/16/2010 |
| 7783870 | Branch target address cache A processor includes an execution unit and instruction sequencing logic that fetches instructions from a memory system for execution. The instruction sequencing logic includes branch logic that outputs predicted branch target addresses for use as instruction fetch a... | 08/24/2010 |
| 7783869 | Accessing branch predictions ahead of instruction fetching A data processing apparatus is disclosed that comprises: a processor for processing a stream of decoded instructions; a prefetch unit for fetching instructions within a stream of instructions from a memory prior to sending said stream of instructions to said process... | 08/24/2010 |
| 7707396 | Data processing system, processor and method of data processing having improved branch target address cache A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating ... | 04/27/2010 |
| 7681021 | Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch A processor has a fetch unit and a branch execution unit. The fetch unit has a branch predictor. The branch predictor has a branch target buffer and a branch direction predictor. A wake value is a number of instruction fetches that is predicted to be performed after... | 03/16/2010 |
| 7676663 | Method, system and program product for pipelined processor having a branch target buffer (BTB) table with a recent entry queue in parallel with the BTB table A method and apparatus enable supplementing a Branch Target Buffer (BTB) table with a recent entry queue that prevents unnecessary removal of valuable BTB table data of multiple entries for another entry. The recent entry queue detects when the startup latency of th... | 03/09/2010 |
| 7640422 | System for reducing number of lookups in a branch target address cache by storing retrieved BTAC addresses into instruction cache A technique for reducing lookups to a branch target address cache (BTAC) is disclosed. In this technique, a branch target address is retrieved from the BTAC in response to a miss in looking up an instruction address in an instruction cache (I-cache). The branch targ... | 12/29/2009 |
| 7546445 | Information processor having delayed branch function with storing delay slot information together with branch history information In correspondence with an address of a branch instruction, a branch target address Apb, a valid bit V as branch history information, and delay slot information POS on the last position of delay slot instructions are stored in a branch target buffer 241. A bra... | 06/09/2009 |
| 7519798 | Utilizing a branch predictor outcome to decide whether to fetch or not to fetch from a branch target buffer A method, system and branch predictor for branch prediction. The system includes a processor core for executing instructions, a branch target buffer for fetching a branch address, and a branch predictor for first predicting a branch of a current instruction address ... | 04/14/2009 |
| 7447882 | Context switching within a data processing system having a branch prediction mechanism A branch target buffer is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries within the branch target buffer and those individual entries are invalidated. ... | 11/04/2008 |
| 7447883 | Allocation of branch target cache resources in dependence upon program instructions within an instruction queue A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10... | 11/04/2008 |
| 7437543 | Reducing the fetch time of target instructions of a predicted taken branch instruction A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instru... | 10/14/2008 |
| 7434037 | System for target branch prediction using correlation of local target histories including update inhibition for inefficient entries An information processing system includes a branch target buffer (BTB) comprising the last next address for the instruction and for receiving an indirect instruction address and providing a BTB predicted target; and next branch target table (NBTT) for storing potent... | 10/07/2008 |
| 7409535 | Branch target prediction for multi-target branches by identifying a repeated pattern An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-ta... | 08/05/2008 |
| 7398377 | Apparatus and method for target address replacement in speculative branch target address cache An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid entry is replaced. If both entries are valid, the least recently used... | 07/08/2008 |
| 7370150 | System and method for managing a cache memory A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and data move and compare operations may be performed efficiently on cached... | 05/06/2008 |
| 7353369 | System and method for managing divergent threads in a SIMD architecture One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetchin... | 04/01/2008 |
| 7350037 | Digital signal processor and digital signal processing method enabling concurrent program download and execution A signal processing device has a program memory for storing program code transferred from an external source under the control of an access control unit having an address counter. The transferred program code is executed by a computational unit having a program coun... | 03/25/2008 |
| 7350062 | Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a branch history). The information processing apparatus, in order to proce... | 03/25/2008 |
| 7346737 | Cache system having branch target address cache A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The BTAC access bits represent a presence of a branch instruction on the ... | 03/18/2008 |
| 7343481 | Branch prediction in a data processing system utilizing a cache of previous static predictions A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12. A static branch prediction cache 30, 32, 34 is provided for storing a most recently encountered static branch prediction such that a sub... | 03/11/2008 |
| 7337271 | Context look ahead storage structures A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing meta-information based on information stored in a memory. A second m... | 02/26/2008 |
| 7328332 | Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740)... | 02/05/2008 |
| 7320066 | Branch predicting apparatus and branch predicting method A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is comple... | 01/15/2008 |
| 7316021 | Switching method in a multi-threaded processor A processor includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The processor, while operating in multithreaded conditio... | 01/01/2008 |
| 7292772 | Method and apparatus for decoding and recording medium for a coded video stream A video decoder reproduces an MP@ML/MPEG-2 video bit stream at an arbitrary speed. When a slice decoder control circuit receives parameters, the slice decoder control circuit sequentially supplies parameters of a picture layer and a write pointer associated with a f... | 11/06/2007 |
| 7284116 | Method and system for safe data dependency collapsing based on control-flow speculation The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provi... | 10/16/2007 |
| 7266676 | Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the tag array provides an index to a corresponding entry in the data array,... | 09/04/2007 |
| 7260684 | Trace cache filtering A cache management logistics controls a transfer of a trace. A first cache couples to the cache management logistics to evict the trace based on a replacement mechanism. A second cache couples to the cache management logistics to receive the trace based on a number ... | 08/21/2007 |
| 7257698 | Instruction buffer and method of controlling the instruction buffer where buffer entries are issued in a predetermined order An instruction buffer of the present invention includes a sequence of instructions arranged in an order determined beforehand, and a buffer including entries arranged in a preselected order for storing the sequence of instructions. Any one of the instructions stored... | 08/14/2007 |
| 7237098 | Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address. Typically the return stack is more accurate. However, if the return stack... | 06/26/2007 |
| 7234046 | Branch prediction using precedent instruction address of relative offset determined based on branch type and enabling skipping A method of predicting and skipping branch instructions for pipelines which need more than one cycle to predict branch direction and branch target addresses in microprocessors and digital signal processors is provided. The address of an instruction executed before t... | 06/19/2007 |
| 7234025 | Microprocessor with repeat prefetch instruction A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preced... | 06/19/2007 |
| 7234041 | Embedded system with instruction prefetching device, and method for fetching instructions in embedded systems In a method for fetching instructions in an embedded system, a predicted one of a set of the instructions stored in a memory device is fetched and is subsequently stored in an instruction buffer when a system bus is in a data access phase. When a processor generates... | 06/19/2007 |
