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| Number | Title | Issue Date |
| 7818552 | Operation, compare, branch VLIW processor A VLIW processor is provided with an architecture which includes fetching and executing circuitry which when combined with operation, compare, branch (OCB) instructions realizes no processing branch penalties. The OCB instructions are provided with two direct branch... | 10/19/2010 |
| 7793084 | Efficient handling of vector high-level language conditional constructs in a SIMD processor The present invention provides an efficient method to implement nested if-then-else conditional statements in a SIMD processor, which requires only one vector compare instruction for both if and else parts of the conditional construct. No stack and stack-handling in... | 09/07/2010 |
| 7451299 | System and method for generating multi-way branches State machines can be used in a scanner and a parser for program compilation. The state machines can be non-table-driven, but rather are encoded directly in bytecodes. A special algorithm can be used to generate the multi-way branch associated with a state in a stat... | 11/11/2008 |
| 7373488 | Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturating operation, a first source having packed data elements and a seco... | 05/13/2008 |
| 7373637 | Method and apparatus for counting instruction and memory location ranges A method, apparatus, and computer instructions in a data processing system for processing instructions and monitoring accesses to memory location ranges. An instruction for execution is identified. A determination is made as to whether the instruction is within a co... | 05/13/2008 |
| 7370151 | Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array ... | 05/06/2008 |
| 7353488 | Flow definition language for designing integrated circuit implementation flows An instance of a flow definition language for designing an integrated circuit implementation flow. The instance of the flow definition language includes a hierarchical collection of stages for a physical chip design. Relational constraints define the execution order... | 04/01/2008 |
| 7353369 | System and method for managing divergent threads in a SIMD architecture One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetchin... | 04/01/2008 |
| 7353505 | Tracing the execution path of a computer program The invention relates to tracing the execution path of a computer program comprising at least one module including a plurality of instructions. At least one of these instructions is a branch instruction. Each branch instruction is identified and evaluated to be one ... | 04/01/2008 |
| 7350110 | Method and system using hardware assistance for continuance of trap mode during or after interruption sequences A method, system, apparatus, and computer program product is presented for processing instructions. A processor is able to receive multiple types of interruptions while executing instructions, such as aborts, faults, interrupts, and traps. A set of processor fields ... | 03/25/2008 |
| 7328429 | Instruction operand tracing for software debug A tool that enables a user to perform instruction operand tracing during debug is presented. While executing microcode on a simulator, a history of register and memory values is saved. A graphic user interface uses these values to present a view of the microcode in ... | 02/05/2008 |
| 7296130 | Method and apparatus for providing hardware assistance for data access coverage on dynamically allocated data A method, apparatus, and computer instructions for generating coverage data for accesses to dynamically allocated data during execution of code in a data processing system. In response to a request to dynamically allocate a memory area for dynamically allocated data... | 11/13/2007 |
| 7293164 | Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions A method, apparatus, and computer instructions for autonomically counting selected branch instructions executed in a processor to improve branch predictions. Counters are provided to count branch instructions that are executed in a processor to collect branch statis... | 11/06/2007 |
| 7290255 | Autonomic method and apparatus for local program code reorganization using branch count per instruction hardware A method, apparatus, and computer instructions for local program reorganization using branch count per instruction hardware. In a preferred embodiment, a hardware counter is used in the present invention to count the number of times a branch is taken when branch ins... | 10/30/2007 |
| 7275246 | Executing programs for a first computer architecture on a computer of a second architecture Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context... | 09/25/2007 |
| 7266673 | Speculation pointers to identify data-speculative operations in microprocessor A microprocessor may include a retire queue and one or more data speculation verification units. The data speculation verification units are each configured to verify data speculation performed on operations. Each data speculation verification unit generates a respe... | 09/04/2007 |
| 7257665 | Branch-aware FIFO for interprocessor data sharing A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to... | 08/14/2007 |
| 7257657 | Method and apparatus for counting instruction execution and data accesses for specific types of instructions A method, apparatus, and computer instructions for processing instructions. Responsive to receiving an instruction for execution in an instruction cache in a processor in the data processing system, a determination is made as to whether an indicator is associated wi... | 08/14/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7234100 | Decoder for trellis-based channel encoding A system and method for decoding a channel bit stream efficiently performs trellis-based operations. The system includes a butterfly coprocessor and a digital signal processor. For trellis-based encoders, the system decodes a channel bit stream by performing operati... | 06/19/2007 |
| 7234043 | Decoding predication instructions within a superscaler data processing system Within a multiple instruction pipeline data processing system which supports predication instructions, program instructions are initially decoded upon the assumption that they are predicated. A predication signal is generated within the instruction decoder stages wh... | 06/19/2007 |
| 7228404 | Managing instruction side-effects A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the represe... | 06/05/2007 |
| 7225309 | Method and system for autonomic performance improvements in an application via memory relocation A method, an apparatus, and a computer program product in a data processing system are presented for using hardware assistance for gathering performance information that significantly reduces the overhead in gathering such information. Performance indicators are ass... | 05/29/2007 |
| 7225434 | Method to collect address trace of instructions executed A method to collect address trace of instructions executed by a processor has been disclosed. An embodiment of the method includes receiving a software program having a set of instructions and performing instrumentation on the software program to determine addresses... | 05/29/2007 |
| 7219213 | Flag bits evaluation for multiple vector SIMD channels execution According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by th... | 05/15/2007 |
| 7210024 | Conditional instruction execution via emissary instruction for condition evaluation Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the condition and an unconditional base instruction operative to perform the ope... | 04/24/2007 |
| 7197630 | Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation A method and system for changing the executable status of an operation following a branch misprediction. In one embodiment, a method may include predicting an execution path of a first conditional branch operation stored in an entry of a trace cache, and in response... | 03/27/2007 |
| 7197586 | Method and system for recording events of an interrupt using pre-interrupt handler and post-interrupt handler A method, apparatus, and computer instructions for providing pre and post handlers to log trace records before entering or after exiting the interrupt handler. A trace record includes a ‘from’ address where the interrupt occurs or where the branch instruction is... | 03/27/2007 |
| 7185367 | Method and system for establishing normal software system behavior and departures from normal behavior Detecting abnormal activity of a software system is based on behavioral information obtained from an instrumented computer program while it executes. As the program executes, it expresses information about the sequence and frequency with which program modules are ca... | 02/27/2007 |
| 7181723 | Methods and apparatus for stride profiling a software application Methods and an apparatus for stride profiling a software application are disclosed. An example system uses a hardware performance counter to report instruction addresses and data addresses associated with memory access instructions triggered by some event, such as a... | 02/20/2007 |
| 7181599 | Method and apparatus for autonomic detection of cache “chase tail” conditions and storage of instructions/data in “chase tail” data structure A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the system. If a selected indicator is associated with the instruction, counting of each event associated... | 02/20/2007 |
| 7170513 | System and method for display list occlusion branching A system and method are provided for conditional branching in a hardware graphics pipeline. Initially, a plurality of graphics commands is received. Condition data is then affected based on at least some of the graphics commands utilizing the hardware graphics pipel... | 01/30/2007 |
| 7167973 | Method and system for performing multi-tests in processors using results to set a register and indexing based on the register A microprocessor, including a plurality of registers and an instruction execution module which is adapted to process a sequence of conditional tests. The module uses an instruction set that has the following instructions: A test-and-condition instruction whic... | 01/23/2007 |
| 7165169 | Speculative branch target address cache with selective override by secondary predictor based on branch instruction type A branch prediction apparatus having a primary predictor and a secondary predictor that selectively overrides the primary predictor based on the type of branch instruction decoded. A branch target address cache in the primary branch predictor speculatively predicts ... | 01/16/2007 |
| 7146473 | Mechanism for ring buffering in an arbitrary-action tracing framework A method for storing a data set having an enabled probe identification component and an associated data component in a buffer, including storing the data set at a current offset if the buffer has sufficient space to store the data set between a current offset and a ... | 12/05/2006 |
| 7143270 | System and method for adding an instruction to an instruction set architecture A processor comprising a feature indicator associated with at least one of a first sequence of one or more instructions, a first register, a second register, and an execution core is provided. The execution core is configured to execute a second instruction to cause... | 11/28/2006 |
| 7140003 | Method and system for specifying sets of instructions for selection by an instruction generator A method for specifying a set of instructions selectable for generation by an instruction generator is disclosed. A class name representative of a class of instructions is identified and concatenated with a unique identifier label, thereby defining a unique singleto... | 11/21/2006 |
| 7137110 | Profiling ranges of execution of a computer program Profiling execution of a program. The program is coded in a mode-dependent instruction set. During a profile-quiescent execution interval, the profile circuitry records no profile information. After a triggering event is detected, the profile circuitry commences a p... | 11/14/2006 |
| 7136992 | Method and apparatus for a stew-based loop predictor A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the expected number of times that a predictor stew value will repeat duri... | 11/14/2006 |
| 7114036 | Method and apparatus for autonomically moving cache entries to dedicated storage when false cache line sharing is detected A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each ... | 09/26/2006 |
