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| Number | Title | Issue Date |
| 8069339 | Microprocessor with microinstruction-specifiable non-architectural condition code flag register A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plur... | 11/29/2011 |
| 8046569 | Processing element having dual control stores to minimize branch latency Embodiments involve an embedded processing element that fetches at least two possible next instructions (control words) in parallel in one cycle, and executes one of them during the following cycle based on the result of a conditional branch test. Embodiments reduce... | 10/25/2011 |
| 7937572 | Run-time selection of feed-back connections in a multiple-instruction word processor A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS1, IS2) arranged for parallel execution of the pl... | 05/03/2011 |
| 7873817 | High speed multi-threaded reduced instruction set computer (RISC) processor with hardware-implemented thread scheduler A reduced instruction set computer (RISC) processor includes a processing core, which is arranged to process a software thread. A hardware-implemented scheduler is arranged to receive respective contexts of a plurality of software threads, to determine a schedule fo... | 01/18/2011 |
| 7620804 | Central processing unit architecture with multiple pipelines which decodes but does not execute both branch paths A central processing unit (CPU) architecture with enhanced branch execution, being substantially a pipelined CPU with multiple pipelines, each pipeline having a plurality of stages, by which all instructions relating directly to a branch instruction of a code execut... | 11/17/2009 |
| 7610473 | Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first operand specifying the initial instruction address of a new thread and... | 10/27/2009 |
| 7574588 | Time-multiplexed speculative multi-threading to support single-threaded applications One embodiment of the present invention provides a system that facilitates interleaved execution of a head thread and a speculative thread within a single processor pipeline. The system operates by executing program instructions using the head thread, and by specula... | 08/11/2009 |
| 7500087 | Synchronization of parallel processes using speculative execution of synchronization instructions A speculative execution capability of a processor is exposed to program control through at least one machine instruction. The at least one machine instruction may be two instructions designed to facilitate synchronization between parallel processes. According to an ... | 03/03/2009 |
| 7454601 | N-wide add-compare-select instruction The present invention relates to a method and system for providing an N-wide add-compare-select instruction includes decoding an instruction as an N-wide add-compare-select instruction and selecting a plurality of branch metrics. The method also includes combining t... | 11/18/2008 |
| 7421572 | Branch instruction for processor with branching dependent on a specified bit in a register A processor such as a parallel hardware-based multithreaded processor (12) is described. The processor (12) can execute a computer instruction that is a branch instruction that causes an instruction sequence in the processor to branch on any specified ... | 09/02/2008 |
| 7409535 | Branch target prediction for multi-target branches by identifying a repeated pattern An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of target addresses representing a history of target addresses for a multi-ta... | 08/05/2008 |
| 7370182 | Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing un... | 05/06/2008 |
| 7363474 | Method and apparatus for suspending execution of a thread until a specified memory access occurs Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. S... | 04/22/2008 |
| 7350061 | Assigning free register to unmaterialized predicate in inverse predicate expression obtained for branch reversal in predicated execution system Described is a method that identifies a predicate expression representing conditions in predicated assembly language instructions that determine a direction of a conditional branch instruction. The predicate expression is employed to enable a transformation to be ma... | 03/25/2008 |
| 7343481 | Branch prediction in a data processing system utilizing a cache of previous static predictions A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12. A static branch prediction cache 30, 32, 34 is provided for storing a most recently encountered static branch prediction such that a sub... | 03/11/2008 |
| 7340587 | Information processing apparatus, microcomputer, and electronic computer An information processing apparatus performing pipeline control includes a first fetch cue fetching a non-branch location instruction, a second fetch cue fetching a branch location instruction, a fetch circuit which carries out arithmetic of a fetch address, fetch i... | 03/04/2008 |
| 7334143 | Computer power conservation apparatus and method that enables less speculative execution during light processor load based on a branch confidence threshold value A computer measures a processor load and configures itself so that a lesser amount of speculative execution is enabled when the processor is lightly loaded than is enabled when the processor is heavily loaded. ... | 02/19/2008 |
| 7328332 | Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740)... | 02/05/2008 |
| 7328329 | Controlling processing of data stream elements using a set of specific function units A device (1) to control processing of data elements (data_i), in which a thread is assigned to each data element (data_i), comprises a first unit (CS), which, during a first cycle, fetches an instruction (cs_ir_s) that is entered in the context of the thread ... | 02/05/2008 |
| 7313655 | Method of prefetching using a incrementing/decrementing counter The present invention provides a pre-fetch controller and a method thereof for efficiently pre-fetching data from a memory device. The method includes initializing a counter value; fetching a data from the memory and subtracting the counter value by a first value wh... | 12/25/2007 |
| 7302556 | Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors A method, apparatus and computer program product are provided for implementing a level bias function for branch prediction control for generating test simulation vectors. User selected options are received for a set of constraints for generating test simulation vect... | 11/27/2007 |
| 7281120 | Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an inter... | 10/09/2007 |
| 7281140 | Digital throttle for multiple operating points A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline. The monitored activity is scaled according to the current operating point of the processor and a power state is determined from the sc... | 10/09/2007 |
| 7281122 | Method and apparatus for nested control flow of instructions using context information and instructions having extra bits A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction multiple data (SIMD) operations. The method and apparatus further incl... | 10/09/2007 |
| 7269693 | Selectively monitoring stores to support transactional program execution One embodiment of the present invention provides a system that selectively monitors store instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processo... | 09/11/2007 |
| 7269694 | Selectively monitoring loads to support transactional program execution One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor... | 09/11/2007 |
| 7269717 | Method for reducing lock manipulation overhead during access to critical code sections One embodiment of the present invention supports execution of a start transactional execution (STE) instruction, which marks the beginning of a block of instructions to be executed transactionally. Upon encountering the STE instruction during execution of a program,... | 09/11/2007 |
| 7263543 | Method for manipulating data in a group of processing elements to transpose the data using a memory stack A method for transposing data in a plurality of processing elements is comprised of a plurality of shifting operations and a plurality of storing operations. The shifting and storing operations are coordinated to enable data to be stored along a diagonal of processi... | 08/28/2007 |
| 7263685 | Synchronizing use of a device by multiple software components in accordance with information stored at the device According to some embodiments, a method is directed to determining via a plurality of flags stored at a PCI device that the PCI device is to perform a first function. The PCI device is shared with a first software component associated with the first function and a s... | 08/28/2007 |
| 7260706 | Branch misprediction recovery using a side memory A mispredicted path side memory is configured to be coupled to a stage in an instruction pipeline. As instructions advance through the pipeline, a result from the stage is stored into the mispredicted path side memory. The result is restored from the mispredicted pa... | 08/21/2007 |
| 7257700 | Avoiding register RAW hazards when returning from speculative execution One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a processor with an in-order architecture, wherein the processor includes a sh... | 08/14/2007 |
| 7245623 | System and method using hierarchical parallel banks of associative memories A system and method provide for efficient classification of long strings of data, such as network messages. The system, which may be a classification engine for use in a network device, is configured to include one or more stages having one or more banks of ternary ... | 07/17/2007 |
| 7242414 | Processor having a compare extension of an instruction set architecture A processor having a compare extension of an instruction set architecture which incorporates a set of high performance floating point operations. The instruction set architecture incorporates a variety of data formats including single precision and double precision ... | 07/10/2007 |
| 7240164 | Folding for a multi-threaded network processor A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write ... | 07/03/2007 |
| 7238218 | Memory prefetch method and system Prefetching data and instructions from a hierarchical memory based upon trajectories and patterns of prior memory fetches. Portions of the data are stored in a slower main memory and are transferred to faster intermediate memory between a requester and the slower ma... | 07/03/2007 |
| 7240185 | Computer system with two debug watch modes for controlling execution of guarded instructions upon breakpoint detection A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be “killedâ... | 07/03/2007 |
| 7240186 | System and method to avoid resource contention in the presence of exceptions A multi-threaded processor is configured to detect excepted instructions from a first program, and to stop fetching younger instructions from that same program, to thereby conserve system resources that can be used by other programs. Each fetched program instruction... | 07/03/2007 |
| 7225299 | Supporting speculative modification in a data cache Method and system for supporting speculative modification in a data cache are provided and described. A data cache comprises a plurality of cache lines. Each cache line includes a state indicator for indicating anyone of a plurality of states, wherein the plurality ... | 05/29/2007 |
| 7203824 | Apparatus and method for handling BTAC branches that wrap across instruction cache lines A branch control apparatus in a microprocessor. The apparatus includes a branch target address cache (BTAC) that caches indications of whether a branch instruction wraps across two cache lines. When an instruction cache fetch address of a first cache line containing... | 04/10/2007 |
| 7200738 | Reducing data hazards in pipelined processors to provide high processor utilization A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions... | 04/03/2007 |
