Did You Know...
...that when IBM conducted a market study of Chester Carlson's invention in 1959, the company concluded that it would take only 5000 units of his new product to saturate the market? IBM therefore declined to be part of the new product introduction. Too bad for IBM. Carlson's invention was the xerography process, and his new product was the beginning of the Xerox Corporation. It is estimated that every day, worldwide, 3,000,000,000 copies are made!!
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| Number | Title | Issue Date |
| 8145889 | Data processing system with branch target addressing using upper and lower bit permutation A data processor or a data processing system used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At t... | 03/27/2012 |
| 8099586 | Branch misprediction recovery mechanism for microprocessors A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this con... | 01/17/2012 |
| 8086829 | Method and apparatus for processing data related to handling interrupts in data processing A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least ... | 12/27/2011 |
| 8069338 | Data processing device and control method for preventing an exception caused by an instruction sent to a peripheral device by a branch source program from occurring during execution of a branch destination program or interrupt program A data processing device includes a program execution section to supply an operation direction signal to a peripheral device based on an executed program and execute a branch operation in response to a branch direction signal, and a branch wait operation section to ... | 11/29/2011 |
| 8019979 | Efficient implementation of branch intensive algorithms in VLIW and superscalar processors An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register has a guard input which allows the ALU to write a result to the regist... | 09/13/2011 |
| 8006078 | Central processing unit having branch instruction verification unit for secure program execution Provided are a central processing unit (CPU) and method for executing a branch instruction of a CPU, which can protect user's data by preventing an error due to a computer virus and a hacker is provided. The CPU includes: a branch instruction verification unit which... | 08/23/2011 |
| 7930525 | Method and apparatus for an efficient multi-path trace cache design A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency... | 04/19/2011 |
| 7877585 | Structured programming control flow in a SIMD architecture One embodiment of a computing system configured to manage divergent threads in a SIMD thread group includes a stack configured to store state information for processing control instructions. A parallel processing unit is configured to perform the steps of determinin... | 01/25/2011 |
| 7836286 | Data processing system to calculate indexes into a branch target address table based on a current operating mode The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension o... | 11/16/2010 |
| 7818551 | Feedback mechanism for dynamic predication of indirect jumps Systems and methods are provided to detect instances where dynamic predication of indirect jumps (DIP) is considered to be ineffective utilizing data collected on the recent effectiveness of dynamic predication on recently executed indirect jump instructions. Illust... | 10/19/2010 |
| 7802080 | Null exception handling A processor 6 is provided with an instruction decoder 18 which is responsive to memory access instructions to determine whether the base register value being used matches a null value and if such a match occurs then branches to a null value exception h... | 09/21/2010 |
| 7765387 | Program counter control method and processor thereof for controlling simultaneous execution of a plurality of instructions including branch instructions using a branch prediction mechanism and a delay instruction for branching A program counter control method controls instructions by an out-of-order method using a branch prediction mechanism and controls an architecture having delay instructions for branching. The method includes the steps of simultaneously committing a plurality of instr... | 07/27/2010 |
| 7761697 | Processing an indirect branch instruction in a SIMD architecture One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetchin... | 07/20/2010 |
| 7711934 | Processor core and method for managing branch misprediction in an out-of-order processor pipeline A processor core and method for managing branch misprediction in an out-of-order processor pipeline. In one embodiment, the pipeline of the processor core includes a front-end instruction fetch portion, a back-end instruction execution portion, and pipeline control ... | 05/04/2010 |
| 7620803 | Data processing device and electronic equipment using pipeline control A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline control. The data processing device includes an instruction queue in which a... | 11/17/2009 |
| 7603544 | Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory ... | 10/13/2009 |
| 7493479 | Method and apparatus for event detection for multiple instruction-set processor A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructio... | 02/17/2009 |
| 7472261 | Method for performing externally assisted calls in a heterogeneous processing complex A method is provided for accessing, by an application running on a first processor, operating system services from an operating system running on a second processor by performing an assisted call. A data plane processor first constructs a parameter area based on the... | 12/30/2008 |
| 7434035 | Method and system for processing instructions in grouped and non-grouped modes An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instru... | 10/07/2008 |
| 7428632 | Branch prediction mechanism using a branch cache memory and an extended pattern cache A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a plurality of compressed representations of these such that when they ... | 09/23/2008 |
| 7415601 | Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an out... | 08/19/2008 |
| 7412592 | Branch instruction control apparatus and control method The branch instruction control apparatus of the present invention is a control apparatus in which a plurality of entries in which data required for the implementation control of the branch instructions is stored in order of decoding successively from the top entry, ... | 08/12/2008 |
| 7386647 | System and method for processing an interrupt in a processor supporting multithread execution A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to the read-only portion of system memory. Upon receipt of an interrupt, ... | 06/10/2008 |
| 7373447 | Multi-port processor architecture with bidirectional interfaces between busses A multi-port processor architecture having a first bus, a second bus and a central processing unit. The central processing unit having a first and second ports coupled to first and second busses respectively. A first bus to second bus bi-directional interface couple... | 05/13/2008 |
| 7370176 | System and method for high frequency stall design A system and method for a high frequency stall design is presented. An issue unit includes a first instruction stage, a second instruction stage, and issue control logic. During a first instruction cycle, the issue unit performs two tasks, which are 1) the instructi... | 05/06/2008 |
| 7370182 | Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing un... | 05/06/2008 |
| 7366885 | Method for optimizing loop control of microcoded instructions A method for optimizing loop control of microcoded instructions includes identifying an instruction as a repetitive microcode instruction such as a move string instruction, for example, having a repeat prefix. The repetitive microcode instruction may include a loop ... | 04/29/2008 |
| 7363477 | Method and apparatus to reduce misprediction penalty by exploiting exact convergence A method and apparatus for executing a selective recovery after a branch misprediction is disclosed. In one embodiment, the instructions following the mispredicted branch point may be saved for selective re-execution in a buffer. Those instructions that wrote to phy... | 04/22/2008 |
| 7353363 | Patchable and/or programmable decode using predecode selection Mechanisms have been developed for providing great flexibility in processor instruction handling, sequencing and execution. In particular, it has been discovered that a configurable predecode mechanism can be employed to select, for respective instruction patterns, ... | 04/01/2008 |
| 7350061 | Assigning free register to unmaterialized predicate in inverse predicate expression obtained for branch reversal in predicated execution system Described is a method that identifies a predicate expression representing conditions in predicated assembly language instructions that determine a direction of a conditional branch instruction. The predicate expression is employed to enable a transformation to be ma... | 03/25/2008 |
| 7340628 | Branch based activity monitoring During execution of a program of computer instructions, the execution of branch instructions is detected, and in response, the activity of processing circuitry during execution of instructions following a branch instruction is measured. Respective information about ... | 03/04/2008 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page int... | 03/04/2008 |
| 7340586 | Data transfer for debugging in data driven type processor processing data packet with data flow program including transfer control bit setting instruction A data-driven type information processor includes a ifinction processor manipulating contents in a data packet, a program storage unit storing a data flow program used by the function processor, and a branch unit controlling data flow whether to allow flow of a data... | 03/04/2008 |
| 7328329 | Controlling processing of data stream elements using a set of specific function units A device (1) to control processing of data elements (data_i), in which a thread is assigned to each data element (data_i), comprises a first unit (CS), which, during a first cycle, fetches an instruction (cs_ir_s) that is entered in the context of the thread ... | 02/05/2008 |
| 7328332 | Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages A processor (1700) including a pipeline (1710, 1740) having a fetch pipeline (1710) with branch prediction circuitry (1840) to supply respective predicted taken target addresses for branch instructions, an execution pipeline (1740)... | 02/05/2008 |
| 7318145 | Random slip generator A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be configurable so that the average frequency of random slips generated by the sys... | 01/08/2008 |
| 7313797 | Uniprocessor operating system design facilitating fast context switching A task stack and a context pointer in a task control block (TCB) are implemented to provide more efficient context switching. Additionally, multiple routines each of which saves or restores a certain combination of volatile registers is implemented. A task can store... | 12/25/2007 |
| 7308562 | System and method for improved branch performance in pipelined computer architectures A system and method for improved branch performance in pipelined computer architectures is presented. Priority bits are set during code execution that corresponds to an upcoming branch instruction. A priority bit may be associated with a register, a resource, or a m... | 12/11/2007 |
| 7302556 | Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors A method, apparatus and computer program product are provided for implementing a level bias function for branch prediction control for generating test simulation vectors. User selected options are received for a set of constraints for generating test simulation vect... | 11/27/2007 |
| 7299369 | Power reduction in microprocessor systems method of preventing an electronic file containing a computer virus from infecting a computer system using the Symbian™ operating system, the method comprising the steps of scanning files using an anti-virus application, and if an infected file is identified, main... | 11/20/2007 |
