Bizarre Patents
Mountable Printable Placard With Headband
A resilient headband in a shape for being mounted on the head of the user. The headband is equipped with a longitudinal slotted member for holding a placard.
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| Number | Title | Issue Date |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7398376 | Instructions for ordering execution in pipelined processes Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory write operations local to a CPU to occur in an arbitrary order, and plac... | 07/08/2008 |
| 7366882 | Address calculation unit for an object oriented processor having differentiation circuitry for selectively operating micro-instructions A processor is provided with a address calculation unit so as to generate addresses for elements of object oriented data structures in one processor clock cycle. ... | 04/29/2008 |
| 7321965 | Integrated mechanism for suspension and deallocation of computational threads of execution in a processor A microprocessor includes a core configured to concurrently execute instructions of a plurality of program threads and a yield instruction, included in the instruction set of the microprocessor. The yield instruction includes an opcode for instructing the microproce... | 01/22/2008 |
| 7313676 | Register renaming for dynamic multi-threading A register renaming technique for dynamic multithreading. One disclosed embodiment includes a register map to store up to M×N values to map M registers for N threads. A set of N values, one per thread, and a set of state bits is associated with each of the M regist... | 12/25/2007 |
| 7281250 | Multi-thread execution method and parallel processor system With a single program divided into a plurality of threads A to C, at the execution of the threads in parallel to each other by a plurality of processors, determination is made of a forkability of a slave thread into other processor in response to a fork instruction ... | 10/09/2007 |
| 7245149 | Dynamic programmable logic array having enable unit A DPLA (dynamic programmable logic array) uses an enable unit for each output line that provides OR-functionality, to eliminate a clock signal in the OR-plane. A clock signal is used only in the AND-plane for pre-charging the product term lines. Such a DPLA operates... | 07/17/2007 |
| 7243210 | Extracted-index addressing of byte-addressable memories A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is t... | 07/10/2007 |
| 7237099 | Multiprocessor system having a plurality of control programs stored in a continuous range of addresses of a common memory and having identification registers each corresponding to a processor and containing data used in deriving a starting address of a CPU-linked interrupt handler program to be executed by the corresponding processor A multiprocessor system has a plurality of CPUs with respective local buses, and a memory which stores a plurality of programs to be executed by the CPUs and is connected to a common bus which can be accessed via the local buses, each local bus being connected to a ... | 06/26/2007 |
| 7222337 | System and method for range check elimination via iteration splitting in a dynamic compiler A range check elimination loop structure is provided. The range check elimination loop structure includes a pre-loop structure based on an original loop structure, where the pre-loop structure is capable of testing indexing expressions for underflow. In addition, a ... | 05/22/2007 |
| 7219218 | Vector technique for addressing helper instruction groups associated with complex instructions The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply, integer-divide, move on integer registers, graphics, floating point calcu... | 05/15/2007 |
| 7203811 | Non-fenced list DMA command mechanism A method and an apparatus are provided for handling a list DMA command in a computer system. The list DMA command relates to an effective address (EA) of a system memory. At least one processor in the system has a local storage. The list DMA command is queued in a D... | 04/10/2007 |
| 7203827 | Link and fall-through address formation using a program counter portion selected by a specific branch address bit A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address of a first set of bytes including a branch instruction and a second a... | 04/10/2007 |
| 7181601 | Method and apparatus for prediction for fork and join instructions in speculative execution A method and apparatus for enabling the speculative forking of a speculative thread is disclosed. In one embodiment, a speculative fork instruction is conditioned by the results of a fork predictor. The fork predictor may issue predictions as to whether or not a spe... | 02/20/2007 |
| 7162618 | Method for enhancing the visibility of effective address computation in pipelined architectures The invention relates to a method to increase the visibility of effective address computation in pipelined architectures. In this method, the current effective address delay of each instruction in the pipeline is calculated. The current effective address delay is us... | 01/09/2007 |
| 7152153 | Bi-directional return register stack recovery from speculative execution of call/return upon branch misprediction A Next Return Target Address stack to maintain return addresses for call and return operations. The invention accommodates both definite return addresses and speculative return address in a single stack. Return addresses are written into the stack and read out of th... | 12/19/2006 |
| 7134124 | Thread ending method and device and parallel processor system Each processor comprises a register for storing start address of a forked child thread and a comparator for detecting that the value of its own program counter is coincident with the start address stored in this register. Each processor sends a thread stop notice to... | 11/07/2006 |
| 7111151 | Microprocessor including microcode unit that only changes the value of control signals required for the current cycle operation for reduced power consumption and method therefor A microprocessor, method and signal-bearing medium for storing a program for executing the method, includes a microcode unit for outputting control signals, for each of a plurality of instructions, required by the microprocessor for executing the instructions. The m... | 09/19/2006 |
| 7092869 | Memory address prediction under emulation Emulation of a guest computer architecture on a host system of another computer architecture. Legacy instructions are translated into translated instructions. If the particular legacy instruction is an operand-setting instruction for storing a value of a precedent o... | 08/15/2006 |
| 7080237 | Register window flattening logic for dependency checking among instructions A technique for flattening architectural register windows into flattened space depending on a current window pointer to a register window is provided. The technique involves converting an n-bit value of a particular register in a register window to an x-bit value de... | 07/18/2006 |
| 7080367 | Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the... | 07/18/2006 |
| 7069549 | Multi-threaded fragment patching A method and system multi-threaded fragment patching. The method provides a link in a self-modifying multi-threaded computer system between a first and a second piece of compiled code where the first piece of compiled code includes a control transfer instruction to ... | 06/27/2006 |
| 7035989 | Adaptive memory allocation This functions maintains two trees: a fast access tree referring to memory blocks of a size most often requested, and a general access tree referring to memory blocks of a size less often requested. After satisfying a request for a memory block, the function adjusts... | 04/25/2006 |
| 7020766 | Processing essential and non-essential code separately A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pi... | 03/28/2006 |
| 7003651 | Program counter (PC) relative addressing mode with fast displacement The invention allows the execution of a PC relative branch instruction with displacement is speeded up without changing the instruction operations of existing processors and without requiring new instructions. The branch target address calculation is made faster by ... | 02/21/2006 |
| 6999911 | Method and apparatus for carrying out circuit simulation In a method and apparatus for carrying out circuit simulation which performs circuit simulation on a circuit to be simulated, a plurality of partial circuits to be inspected for equivalence in order to check if they exhibit equivalent operational characteristics are... | 02/14/2006 |
| 6976158 | Repeat instruction with interrupt A processor for processing an interruptible repeat instruction is provided. The repeat instruction may include an immediate operand specifying a loop count value corresponding to the number of times that the loop is to be repeated. Alternatively, the repeat instruct... | 12/13/2005 |
| 6965987 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose i... | 11/15/2005 |
| 6964026 | Method of updating a semiconductor design A microprocessor, method and signal-bearing medium for storing a program for executing the method, includes a microcode unit for outputting control signals, for each of a plurality of instructions, required by the microprocessor for executing the instructions. The m... | 11/08/2005 |
| 6957304 | Runahead allocation protection (RAP) A method and apparatus are described for protecting cache lines allocated to a cache by a run-ahead prefetcher from premature eviction, preventing thrashing. The invention also prevents premature eviction of cache lines still in use, such as lines allocated by the r... | 10/18/2005 |
| 6957319 | Integrated circuit with multiple microcode ROMs Integrated circuits having multiple independently accessible microcode ROMs. An integrated circuit may include a microcode unit and a plurality of microcode ROMs fabricated within the same integrated circuit. The microcode unit may be configured to receive a microco... | 10/18/2005 |
| 6957322 | Efficient microcode entry access from sequentially addressed portion via non-sequentially addressed portion A microcode instruction unit for a processor may include a microcode memory having entries for storing microcode instructions. A decoder for the microcode memory may decode microcode addresses to select entries of the microcode memory. A microcode entry point genera... | 10/18/2005 |
| 6928533 | Data processing system and method for implementing an efficient out-of-order issue mechanism An out-of-order issue mechanism for a data processing system allows two out-of-order instructions to be issued to independent “pipes” from a window of four instructions currently queued for execution. If the two pipes execute floating pipe operations, dependenci... | 08/09/2005 |
| 6918025 | IC with wait state registers A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of ... | 07/12/2005 |
| 6918028 | Pipelined processor including a loosely coupled side pipe A digital data processor having a main pipeline to which a side pipe is loosely coupled. In particular, the side pipe is coupled to the main pipeline at a point after which an instruction entering the side pipe cannot cause an exception. When such an instruction ent... | 07/12/2005 |
| 6915413 | Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a w... | 07/05/2005 |
| 6880150 | PROCESSOR FOR EXECUTING INSTRUCTIONS IN UNITS THAT ARE UNRELATED TO THE UNITS IN WHICH INSTRUCTIONS ARE READ, AND A COMPILER, AN OPTIMIZATION APPARATUS, AN ASSEMBLER, A LINKER, A DEBUGGER AND A DISASSEMBLER FOR SUCH PROCESSOR When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the... | 04/12/2005 |
| 6851033 | Memory access prediction in a data processing apparatus The present invention relates to techniques for predicting memory access in a data processing apparatus and particular to a technique for determining whether a data item to be accessed crosses an address boundary and will hence require multiple memory accesses. An e... | 02/01/2005 |
| 6779100 | Method and device for address translation for compressed instructions A computer system for storing corresponding instruction blocks in a compressed form in a main memory and in an uncompressed form in an instruction cache. The instruction cache line addresses for the uncompressed instruction blocks in the instruction cache have an al... | 08/17/2004 |
| 6775764 | Search function for data lookup A SEARCH function preferably built into the instruction set of a microprocessor for quickly and efficiently searching a plurality of memory locations. Data from a significant number of memory locations is searched in a very short period of time, using a minimal numb... | 08/10/2004 |
