Did You Know...
...that one person who claimed to be the inventor of the television is Russian emigre Vladimir Zworykin? In 1929 David Sarnoff, founder of RCA, asked Zworykin what it would take to develop TV for commercial use. He said: a year and a half and $100,000. In reality, it took 20 years and $50 million! Before his death in 1982 at the age of 92, Zworykin said of his invention: "The technique is wonderful. It is beyond my expectations. But the programs! I would never let my children even come close to this thing."
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| Number | Title | Issue Date |
| 8190863 | Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ens... | 05/29/2012 |
| 8181004 | Selecting a resource management policy for a resource available to a processor Embodiments include a device and a method. In an embodiment, a device provides a resource manager operable to select a resource management policy likely to provide a substantially optimum execution of an instruction group by comparing an execution of the instruction... | 05/15/2012 |
| 8145887 | Enhanced load lookahead prefetch in single threaded mode for a simultaneous multithreaded microprocessor A method, system, and computer program product are provided for enhancing the execution of independent loads in a processing unit. A processing unit detects if a long-latency miss associated with a load instruction has been encountered. Responsive to a long-latency ... | 03/27/2012 |
| 8145888 | Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a second instruction mode. In the first instruction mode instructions have respective field... | 03/27/2012 |
| 8122231 | Software selectable adjustment of SIMD parallelism Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a... | 02/21/2012 |
| 8086828 | Multiprocessor computing systems with heterogeneous processors Heterogeneous processors can cooperate for distributed processing tasks in a multiprocessor computing system. Each processor is operable in a “compatible” mode, in which all processors within a family accept the same baseline command set and produce identical re... | 12/27/2011 |
| 8041930 | Data processing apparatus and method for controlling thread access of register sets when selectively operating in secure and non-secure domains The data processing apparatus has processing logic for performing data processing operations and a register bank for storing data associated with the processing logic. The register bank has at least one register group, each register group having a plurality of regis... | 10/18/2011 |
| 8032737 | Methods and apparatus for handling switching among threads within a multithread processor A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corre... | 10/04/2011 |
| 8006077 | Thread migration control based on prediction of migration overhead A processing system features a first processing core to operate in a first node, a second processing core to operate in a second node, and random access memory (RAM) responsive to the first and second processing cores. The processing system also features control log... | 08/23/2011 |
| 7996659 | Microprocessor instruction that allows system routine calls and returns from all contexts An apparatus comprises register means for storing a return context upon initiation of a supervisor call instruction and restoring means to restore a privilege level and status register upon execution of a supervisor return instruction. The supervisor call instructio... | 08/09/2011 |
| 7996660 | Software controlled CPU pipeline protection A processor in a digital system executes instructions in an instruction execution pipeline. The processor detects a pipeline protection directive while executing instructions and sets a pipeline protection mode in accordance with the directive. The processor then co... | 08/09/2011 |
| 7984278 | Hardware resource having an optimistic policy and a pessimistic policy Processor resource management devices and methods are disclosed. In some implementations, a device includes a processor, a hardware resource, and a resource manager operable to compare a first execution of one or more instructions pursuant to an optimistic resource ... | 07/19/2011 |
| 7979685 | Multiple instruction execution mode resource-constrained device A resource-constrained device comprises a processor configured to execute multiple instruction streams comprising multiple instructions having an opcode and zero or more operands. Each of the multiple instruction streams is associated with one of multiple instructio... | 07/12/2011 |
| 7975131 | Processor lock A processor having multiple distinct instruction sets is disclosed where one set, a default set, is always available for execution while a second set is only available once a valid control code is externally supplied to the processor to effectively “unlock” and ... | 07/05/2011 |
| 7971042 | Microprocessor system and method for instruction-initiated recording and execution of instruction sequences in a dynamically decoupleable extended instruction pipeline Systems and methods for recording instruction sequences in a microprocessor having a dynamically decoupleable extended instruction pipeline. A record instruction including a record start address is sent to the extended pipeline. The extended pipeline thus begins rec... | 06/28/2011 |
| 7971043 | Electronic system and method for changing number of operation stages of a pipeline An electronic system includes a pipeline having a first number of pipeline stages coupled in series, a pipeline control unit, and a logic engine, wherein each pipeline stage in the pipeline is for outputting data to a next pipeline stage at each cycle of a clock sig... | 06/28/2011 |
| 7949860 | Multi thread processor having dynamic reconfiguration logic circuit A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads (i) causes the execution of a ... | 05/24/2011 |
| 7904704 | Instruction dispatching method and apparatus A system, apparatus and method for instruction dispatch on a multi-thread processing device are described herein. The instruction dispatching method includes, in an instruction execution period having a plurality of execution cycles, successively fetching and issuin... | 03/08/2011 |
| 7904703 | Method and apparatus for idling and waking threads by a multithread processor A system, apparatus and method for idling and waking threads by a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for idling and waking threads including a scheduler configured to deter... | 03/08/2011 |
| 7877584 | Predictive processor resource management Embodiments include a device and a method. In an embodiment, a device includes a processor having an associated hardware resource and operable to execute an instruction group. The device also includes a resource manager operable to implement a resource management po... | 01/25/2011 |
| 7844805 | Portable processing device having a modem selectively coupled to a RISC core or a CISC core A processor for a portable electronic device. The processor includes a RISC (reduced instruction set computing) core a CISC (complex instruction set computing) core, a video accelerator circuit and an audio accelerator circuit. Each of the video and audio accelerato... | 11/30/2010 |
| 7836285 | Implementation of variable length instruction encoding using alias addressing A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code se... | 11/16/2010 |
| 7836284 | Microprocessor with automatic selection of processing parallelism mode based on width data of instructions Automatic selective power and energy control of one or more processing elements matches a degree of parallelism to a monitored condition, in a highly parallel programmable data processor. For example, logic of the parallel processor detects when program operations (... | 11/16/2010 |
| 7809932 | Methods and apparatus for adapting pipeline stage latency based on instruction type Processor pipeline controlling techniques are described which take advantage of the variation in critical path lengths of different instructions to achieve increased performance. By examining a processor's instruction set and execution unit implementation's critical... | 10/05/2010 |
| 7793083 | Processor and system for selectively disabling secure data on a switch A processor (10) manages, in an instruction management unit (103) and a data attribute management unit (105), secure attributes indicating whether instruction code and data stored in an instruction cache (102) and a data cache (104... | 09/07/2010 |
| 7783866 | Method and apparatus for executing instrumentation code using processor instructions A computer implemented method, apparatus and computer program product for processing instructions. A determination is made as to whether an instruction is a start instrumentation instruction in response to identifying the instruction for execution while executing th... | 08/24/2010 |
| 7779239 | User opt-in processor feature control capability A processor includes a feature control unit to enable or disable one or more processor features individually in response to a user selectable setting. The feature control unit is adapted to disable the processor feature(s) if the user setting has not been updated in... | 08/17/2010 |
| 7761696 | Quiescing and de-quiescing point-to-point links Methods and apparatus to quiesce and/or de-quiesce links (such as point-to-point link) in a multi-processor system are described. In one embodiment, one or more bits are modified to indicate the status of quiesce/dequiesce processes. ... | 07/20/2010 |
| 7725693 | Execution optimization using a processor resource management policy saved in an association with an instruction group Embodiments include a device and a method. In an embodiment, a device provides a resource manager operable to select a resource management policy likely to provide a substantially optimum execution of an instruction group by comparing an execution of the instruction... | 05/25/2010 |
| 7711933 | Exploiting unused configuration memory cells A programmable device having a processing core is configured to use a subset of configuration memory cells as read/write memory. The subset of memory cells is a don't care set that includes configuration memory cells that can be set or reset without modifying the fu... | 05/04/2010 |
| 7694114 | Software selectable adjustment of SIMD parallelism Selective power control of one or more processing elements matches a degree of parallelism to requirements of a task performed in a highly parallel programmable data processor. For example, when program operations require less than the full width of the data path, a... | 04/06/2010 |
| 7647486 | Method and system having instructions with different execution times in different modes, including a selected execution time different from default execution times in a first mode and a random execution time in a second mode A method and system for controlling timing in a processor is disclosed. In one aspect of the present invention, the method comprises fetching a plurality of instructions, wherein each instruction has a first default execution time during a first condition, and where... | 01/12/2010 |
| 7647487 | Instruction-associated processor resource optimization Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction block in a first processor. The method also applies a second resource... | 01/12/2010 |
| RE41012 | Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the automatic modification of the register addressing is not tied to a single ... | 11/24/2009 |
| 7603543 | Method, apparatus and program product for enhancing performance of an in-order processor with long stalls A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the prese... | 10/13/2009 |
| 7594102 | Method and apparatus for vector execution on a scalar machine A processor that can execute instructions in either scalar mode or vector mode. In scalar mode, instructions are executed once per fetch. In vector mode, instructions are executed multiple times per fetch. In vector mode, the processor recognizes scalar variables an... | 09/22/2009 |
| 7539852 | Processor resource management Embodiments include a device and a method. In an embodiment, a device provides a resource manager operable to select a resource management policy likely to provide a substantially optimum execution of an instruction group by comparing an execution of the instruction... | 05/26/2009 |
| 7529916 | Data processing apparatus and method for controlling access to registers A data processing apparatus and method are provided for controlling access to registers. The data processing apparatus comprises a processing unit for performing data processing operations on data values, the processing unit having a plurality of modes of operation.... | 05/05/2009 |
| 7451298 | Processing exceptions from 64-bit application program executing in 64-bit processor with 32-bit OS kernel by switching to 32-bit processor mode One embodiment of the present invention provides a system that uses an M-bit operating system (OS) kernel to support N-bit user processes. During operation, the system receives an exception. Note that the exception can be any event that needs to be handled by execut... | 11/11/2008 |
| 7447880 | Processor with internal memory configuration A processor comprises an arithmetic unit for processing operands, a register memory for storing operands with a register memory space and a register memory configuration unit. The register memory configuration unit is designed to configure the register memory such t... | 11/04/2008 |
