Bizarre Patents
Pillow with retractable umbrella
A pillow assembly having a supporting assembly and a retractable umbrella assembly that is easily transportable and allows a user to support his/her head while covering their face from sunlight.
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| Number | Title | Issue Date |
| 8171268 | Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectors A technique for managing context state information enables a reduced number of save and restore operations. At least one embodiment includes a plurality of save area segments to store a plurality of machine context state information, which can be saved into the segm... | 05/01/2012 |
| 8161273 | Method and apparatus for programmatically rewinding a register inside a transaction Embodiments of the present invention provide a system that allocates registers in a processor. The system starts by commencing a transaction, wherein commencing the transaction involves preserving a pre-transactional state of registers in a first register file. The ... | 04/17/2012 |
| 8151095 | System and method for context migration across CPU threads One embodiment of the present invention sets forth a technique for associating arbitrary parallel processing unit (PPU) contexts with a given central processing unit (CPU) thread. The technique introduces two operators used to manage the PPU contexts. The first oper... | 04/03/2012 |
| 8131983 | Method, apparatus and article of manufacture for timeout waits on locks Embodiments of the invention provide techniques for performing timeout waits of process threads. Generally, a thread requesting access to locked resource sends a timeout request to a timeout handler process, and then goes to sleep. The timeout request is received by... | 03/06/2012 |
| 8108662 | Checkpointing a hybrid architecture computing system A method, apparatus, and program product checkpoint an application in a parallel computing system of the type that includes a plurality of hybrid nodes. Each hybrid node includes a host element and a plurality of accelerator elements. Each host element may include a... | 01/31/2012 |
| 8095782 | Multiple simultaneous context architecture for rebalancing contexts on multithreaded processing cores upon a context change Graphics processing elements are capable of processing multiple contexts simultaneously, reducing the need to perform time consuming context switches compared with processing a single context at a time. Processing elements of a graphics processing pipeline may be co... | 01/10/2012 |
| 8082426 | Support of a plurality of graphic processing units Included are systems and methods for supporting a plurality of Graphics Processing Units (GPUs). At least one embodiment of a system includes a context status register configured to send data related to a status of at least one context and a context switch configura... | 12/20/2011 |
| 8082427 | Multithread handling A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coup... | 12/20/2011 |
| 8041929 | Techniques for hardware-assisted multi-threaded processing Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2c registers for each thread. A thread ID is rece... | 10/18/2011 |
| 8041754 | Establishing thread priority in a processor or the like In a multi-threaded processor, one or more variables are set up in memory (e.g., a register) to indicate which of a plurality of executable threads has a higher priority. Once the variable is set, several embodiments are presented for granting higher priority proces... | 10/18/2011 |
| 8032736 | Methods, apparatus and articles of manufacture for regaining memory consistency after a trap via transactional memory Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap... | 10/04/2011 |
| 8019978 | Unit status reporting protocol A unit status reporting protocol may also be used for context switching, debugging, and removing deadlock conditions in a processing unit. A processing unit is in one of five states: empty, active, stalled, quiescent, and halted. The state that a processing unit is ... | 09/13/2011 |
| 8006076 | Processor and program execution method capable of efficient program execution A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select ... | 08/23/2011 |
| 7991983 | Register set used in multithreaded parallel processor architecture A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads or contexts. The processor maintains execution threads. The... | 08/02/2011 |
| 7987346 | Method and apparatus for assigning thread priority in a processor or the like In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting count... | 07/26/2011 |
| 7979684 | Method and context switch device for implementing design-for-testability functionality of latch-based register files A method of changing execution contexts is provided that includes receiving a context selection input. In a first clock phase, the method includes shifting data from a first latch element of a normal execution context to a second latch element of the normal executio... | 07/12/2011 |
| 7971041 | Method and system for register management A system and method of allocating registers in a register array to multiple workloads is disclosed. The method identifies an incoming workload as belonging to a first process group or a second process group, and allocates one or more target registers from the regist... | 06/28/2011 |
| 7971040 | Method and device for saving and restoring a set of registers of a microprocessor in an interruptible manner The disclosure relates to a method for executing by a processor an instruction for saving/restoring several internal registers of the processor. The method comprises breaking down the saving/restoring instruction to generate micro-instructions for saving/restoring t... | 06/28/2011 |
| 7962731 | Backing store buffer for the register save engine of a stacked register file A Backing Store Buffer is interposed between a Physical Register File and the Backing Store in a stacked register file architecture. A Register Save Engine temporarily stores data from registers in the Physical Register File allocated to inactive procedures on-chip,... | 06/14/2011 |
| 7962732 | Instruction processing apparatus An instruction processing apparatus includes a thread execution processing section executing threads each including plural instructions, a register file including a register window having plural registers, a current window pointer indicating a position of the regist... | 06/14/2011 |
| 7937571 | Information-processing apparatus and activation method and program for activating an operating system in a short period of time An information-processing apparatus including an execution-state holding unit that stores an execution state of a program executed by a computer, an execution-state saving unit configured to store the execution state in effect upon execution of the program at a pred... | 05/03/2011 |
| 7930524 | Method for executing a 32-bit flat address program during a system management mode interrupt A method and system for executing 32-bit flat address programs during a System Management Interrupt. The system provides a 16-bit SMI routine that is given control when an SMI occurs. That routine initially saves the state of the processor and then executes an instr... | 04/19/2011 |
| 7921281 | Processor and program execution method capable of efficient program execution A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select ... | 04/05/2011 |
| 7904702 | Compound instructions in a multi-threaded processor A multi-threaded processor determines which threads to execute, switches between execution of threads in dependence on the determination, each thread being coupled to a respective register for storing the state of the thread and used in executing instructions on the... | 03/08/2011 |
| 7877583 | Method and apparatus for assigning thread priority in a processor or the like In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting count... | 01/25/2011 |
| 7873816 | Pre-loading context states by inactive hardware thread in advance of context switch A circuit arrangement and method utilize thread pair context caching, where a pair of hardware threads in a multithreaded processor, which are each capable of executing a process, are effectively paired together, at least temporarily, to perform context switching op... | 01/18/2011 |
| 7849298 | Enhanced processor virtualization mechanism via saving and restoring soft processor/system states A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a m... | 12/07/2010 |
| 7849297 | Software emulation of directed exceptions in a multithreading processor A multithreading microprocessor has a plurality of thread contexts (TCs) each including sufficient state, such as general purpose registers and program counter, to execute a separate thread of execution as one of a plurality of symmetric processors controlled by a m... | 12/07/2010 |
| 7844804 | Expansion of a stacked register file using shadow registers One or more Shadow Register Files (SRF) are interposed between a Physical Register File (PRF) and a Backing Store (BS) in a shadow register file system. The SRFs comprise dual-port registers connected serially in a chain of arbitrary depth from the PRF. A Register S... | 11/30/2010 |
| 7805594 | Multithread processor and register control method The present invention relates to a multithread processor, and this multithread processor comprises a plurality of register windows each provided for each of threads and capable of storing data to be used for instruction processing in an arithmetic unit, a work regis... | 09/28/2010 |
| 7757070 | Methods, apparatuses, and system for facilitating control of multiple instruction threads A system, apparatus and method for multithread handling on a multithread processing device are described herein. Embodiments of the present invention provide a multithread processing device for multithread handling including a plurality of registers operatively coup... | 07/13/2010 |
| 7743237 | Register file bit and method for fast context switch A register file bit includes a primary latch and a secondary latch with a feedback path and a context switch mechanism that allows a fast context switch when execution changes from one thread to the next. A bit value for a second thread of execution is stored in the... | 06/22/2010 |
| 7739484 | Instruction encoding to indicate whether to store argument registers as static registers and return address in subroutine stack A method and apparatus provide means for saving and restoring processor register values and allocating and deallocating stack memory. A first field of a save instruction encodes whether a value in a register of a processor is saved as a static value. A second field ... | 06/15/2010 |
| 7711932 | Scalable rename map table recovery Checkpoints may be used to recover from branch mispredictions using scalable rename map table recovery. ... | 05/04/2010 |
| 7698540 | Dynamic hardware multithreading and partitioned hardware multithreading In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thre... | 04/13/2010 |
| 7694113 | Method for translating instructions in a speculative microprocessor A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of... | 04/06/2010 |
| 7685409 | On-demand multi-thread multimedia processor A device includes a multimedia processor that can concurrently support multiple applications for various types of multimedia such as graphics, audio, video, camera, games, etc. The multimedia processor includes configurable storage resources to store instructions, d... | 03/23/2010 |
| 7681020 | Context switching and synchronization A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the... | 03/16/2010 |
| 7657728 | Register file backup queue Systems and methods are disclosed for maintaining an accurate program-visible machine state of a computer. A backup system and method is provided in order to return the visual state of the computer to a previous state if an instruction generates an exception. In an ... | 02/02/2010 |
| 7640421 | Method and system for determining context switch state A method and apparatus for automatically generating a list of circuit elements, such as registers, to be context switched designed to avoid the omission of elements that must be context switched are provided. The method generally involves creating a list of potentia... | 12/29/2009 |
