Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 8185724 | Monitoring values of signals within an integrated circuit An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more s... | 05/22/2012 |
| 8166284 | Information processing device An information processing device having a function for efficiently debugging a parallel processing program by controlling snoop operation is provided. The information processing device is so configured that the following is implemented: the setting for receiving a s... | 04/24/2012 |
| 8140832 | Single step mode in a software pipeline within a highly threaded network on a chip microprocessor A hardware thread is selectively forced to single step the execution of software instructions from a work packet granule. A “single step” packet is associated with a work packet granule. The work packet granule, with the associated “single step” packet, is d... | 03/20/2012 |
| 8127118 | Microarchitecture, method and computer program product for efficient data gathering from a set of trace arrays An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a... | 02/28/2012 |
| 8103860 | Optional function multi-function instruction A method, system and program product for executing a multi-function instruction in a computer system by specifying, via the multi-function instruction, either a capability query or execution of a selected function of one or more optional functions, wherein the selec... | 01/24/2012 |
| 8090933 | Methods computer program products and systems for unifying program event recording for branches and stores in the same dataflow The present invention relates to a method for the unification of PER branch and PER store operations within the same dataflow. The method comprises determining a PER range, the PER range comprising a storage area defined by a designated storage starting area and a d... | 01/03/2012 |
| 8074059 | System and method for performing deterministic processing A system and method is provided for performing deterministic processing on a non-deterministic computer system. In one example, the system forces execution of one or more computer instructions to execute within a constant execution time. A deterministic engine, if n... | 12/06/2011 |
| 8060730 | Selective MISR data accumulation during exception processing A plurality of test points are located at predetermined circuit nodes in a processing system. Test code which includes a set of software-controllable interrupts is executed using a multiple input shift register (MISR) to generate a MISR signature. One or more select... | 11/15/2011 |
| 8010774 | Breakpointing on register access events or I/O port access events A data processing system is provided with breakpoint circuitry having breakpoint registers which can specify a variety of different types of breakpoint conditions. These breakpoint conditions include register access breakpoints which are triggered when an access is ... | 08/30/2011 |
| 7996658 | Processor system and method for monitoring performance of a selected task among a plurality of tasks A processor system includes a processor to execute a plurality of tasks by switching to one another, a task ID storage section to store a task ID to identify a task executed in the processor, an evaluation ID storage section to store an evaluation ID to be compared ... | 08/09/2011 |
| 7987345 | Performance monitors in a multithreaded processor architecture A system comprising a plurality of execution units configured to execute, at least in part, a plurality of instruction threads; a plurality of performance monitors, each performance monitor being configured to collect performance information related to the execution... | 07/26/2011 |
| 7958342 | Methods for optimizing computer system performance counter utilization A Nyquist sampling frequency is determined for performance counter events to be measured. Based on the Nyquist sampling frequencies, a schedule for measuring the performance counter events is determined. The performance counter event measurements are then conducted ... | 06/07/2011 |
| 7941652 | Apparatus and computer program product for implementing atomic data tracing A method, apparatus and computer program product are provided for implementing atomic data tracing in a processor system including an auxiliary processor unit (APU) coupled to a central processor unit (CPU). The auxiliary processor unit (APU) processes a trace instr... | 05/10/2011 |
| 7917738 | Method and base chip for monitoring the operation of a microcontroller unit To enable a method and a base chip (200) for monitoring, by means of at least one base chip (200), the operation of at least one microcontroller unit (300) that is intended for at least one application and is associated with a system (100... | 03/29/2011 |
| 7908465 | Hardware emulator having a selectable write-back processor unit A method and apparatus for emulating a hardware design comprising an instruction execution unit for executing at least one instruction, a memory for providing data to the instruction execution unit for processing into an output bit, and a write enable logic for cont... | 03/15/2011 |
| 7904701 | Activating a design test mode in a graphics card having multiple execution units to bypass a host cache and transfer test instructions directly to an instruction cache Provided are a method and system for activating a design test mode in a graphics card having multiple execution units. A design test mode is activated in a graphics module comprising multiple execution units coupled to a cache on a bus. The bus is configured to retu... | 03/08/2011 |
| 7895421 | Mechanism for using performance counters to identify reasons and delay times for instructions that are stalled during retirement A system and method of accounting for lost clock cycles in a microprocessor. A method includes detecting a first reason which prevents exit of an entry from an instruction retirement queue, and incrementing a first count corresponding to the first reason, wherein th... | 02/22/2011 |
| 7890737 | Microcomputer and functional evaluation chip A microcomputer for functioning according to operation modes includes; a mode counter that counts the number of times of level change in a signal applied to a mode setting terminal; a mode decoder that decodes output data of the mode counter to output a mode signal,... | 02/15/2011 |
| 7870370 | Determining thermal characteristics of instruction sets Methods, apparatus, and products for determining thermal characteristics of instruction sets comprising one or more computer program instructions executed by a computer processor are disclosed that include tracking, in a performance counter, a number of classes of i... | 01/11/2011 |
| 7865703 | Method and apparatus for executing instrumentation code within alternative processor resources A computer implemented method, apparatus, and computer program product for executing instructions. A determination is made as to whether a processor executing a plurality of instructions is in an instrumentation mode. The processor has a normal set of resources and ... | 01/04/2011 |
| 7865704 | Selective instruction breakpoint generation based on a count of instruction source events A method includes generating an instruction address value in response to an instruction source event. The method further includes selectively generating a breakpoint request based on the instruction source event and responsive to a comparison of the instruction addr... | 01/04/2011 |
| 7861070 | Trace compression method for debug and trace interface wherein differences of register contents between logically adjacent registers are packed and increases of program counter addresses are categorized The present invention proposed a trace compression method for a debug and trace interface of a microprocessor, in which the debug and trace interface is associated with a plurality of registers for storing data. The trace compression method comprises the steps of: (... | 12/28/2010 |
| 7856427 | System and method for suspending transactions being executed on databases A database management system managing one or more databases to suspend access to at least one selected database by one or more processes or applications (e.g., message processing programs, batch messaging programs, etc.). In some instances, the one or more databases... | 12/21/2010 |
| 7849296 | Monitoring control for monitoring at least two domains of multi-domain processors There is provided a method of controlling a monitoring function of a processor, the processor being operable in at least two domains, comprising a first domain and a second domain, the first and second domains each comprising at least one mode, the method comprising... | 12/07/2010 |
| 7840787 | Method and apparatus for non-deterministic incremental program replay using checkpoints and syndrome tracking Methods and apparatus are provided for non-deterministic incremental program replay using checkpoints and syndrome tracking. Replay of a program proceeds by, for a given execution of the program, recording one or more checkpoints of the program, the one or more chec... | 11/23/2010 |
| 7836283 | Data acquisition messaging using special purpose registers A method provides a data acquisition message of a data processing system to an external port thereof. Configuration information is written to a configuration register. It is determined if the configuration information identifies a data acquisition operation. If the ... | 11/16/2010 |
| 7831814 | Monitoring a microprocessor programme by sending time-trackable messages The invention concerns a monitoring device (18′, 18″) integrated to the chip of a microprocessor (12) executing a series of instructions comprising message calculating means (36) for upon each execution of an instruction, producing a corresp... | 11/09/2010 |
| 7831815 | Data processing apparatus and method for identifying sequences of instructions A data processing apparatus is provided comprising a processing unit for executing instructions, a cache structure for storing instructions retrieved from memory for access by the processing unit, and profiling logic for identifying a sequence of instructions that i... | 11/09/2010 |
| 7831816 | Non-destructive sideband reading of processor state information A processor receives a command via a sideband interface on the processor to read processor state information, e.g., CPUID information. The sideband interface provides the command information to a microcode engine in the processor that executes the command to retriev... | 11/09/2010 |
| 7827391 | Method and apparatus for single-stepping coherence events in a multiprocessor system under software control An apparatus and method are disclosed for single-stepping coherence events in a multiprocessor system under software control in order to monitor the behavior of a memory coherence mechanism. Single-stepping coherence events in a multiprocessor system is made possibl... | 11/02/2010 |
| 7805593 | Real-time performance monitoring using a system implemented in an integrated circuit Apparatus and method for performance monitoring is described. Instances of performance monitors are loaded into configurable resources. The performance monitors are coupled to a processor via an auxiliary processor unit or a debug port to obtain processor pipeline e... | 09/28/2010 |
| 7797518 | Generating instruction sets for compacting long instructions A method of generating at least one instruction set from a plurality of program instructions, said plurality of program instructions comprising a plurality of instruction fields each of said instruction fields operable on decoding to generate control signals for tra... | 09/14/2010 |
| 7783865 | Conditional data watchpoint management A method, system and computer program product for managing a conditional data watchpoint in a set of instructions being traced is shown in accordance with illustrative embodiments. In one particular embodiment, the method comprises initializing a conditional data wa... | 08/24/2010 |
| 7778985 | System and method for suspending transactions being executed on databases A database management system managing one or more databases to suspend access to at least one selected database by one or more processes or applications (e.g., message processing programs, batch messaging programs, etc.). In some instances, the one or more databases... | 08/17/2010 |
| 7779238 | Method and apparatus for precisely identifying effective addresses associated with hardware events A system and method for precisely identifying an instruction causing a performance-related event is disclosed. The instruction may be detected while in a pipeline stage of a microprocessor preceding a writeback stage and the microprocessor's architectural state may ... | 08/17/2010 |
| 7752425 | Data processing apparatus having trace and prediction logic A data processing apparatus is disclosed comprising: trace logic for monitoring behavior of a portion of said data processing apparatus; and prediction logic operable to provide at least one prediction as to at least one step of said behavior of said portion of said... | 07/06/2010 |
| 7747844 | Acquiring instruction addresses associated with performance monitoring events Systems, methodologies, media, and other embodiments associated with acquiring instruction addresses associated with performance monitoring events are described. One exemplary system embodiment includes logic for recording instruction and state data associated with ... | 06/29/2010 |
| 7743236 | Reconfigurable processor The present invention provides a reconfigurable processing apparatus enabling clusters to utilize a shared functional unit by using data and a validity signal received from the clusters by way of a network therebetween. In the reconfigurable processing apparatus com... | 06/22/2010 |
| 7725692 | Compact representation of instruction execution path history A method of representing instruction execution path history is provided. The method in one aspect may include gathering information associated with a current instruction, the information including at least a target address. Previously computed bits representing exec... | 05/25/2010 |
| 7707395 | Data processing system with trace co-processor The present invention relates to a processing device and a tracing system and method for providing to an external debugging device a trace information relating to an application program. A trace processor (40) is provided in order to relieve a main processor ... | 04/27/2010 |
