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| Number | Title | Issue Date |
| 8145886 | Changing processor functions by changing function information An information processing equipment comprises: a processor configured to refer to a function information indicating an assigned function and to execute a firmware code corresponding to the function information; and a memory in which the firmware code and the functio... | 03/27/2012 |
| 8099585 | Predicated execution using operand predicates Full predication of instruction execution is provided by operand predicates, where each operand has an associated predicate bit intuitively indicating the validity of the operand value. In a programmable processor supporting operand predication, an instruction will ... | 01/17/2012 |
| 8082425 | Reliable execution using compare and transfer instruction on an SMT machine A system and method for efficient reliable execution on a simultaneous multithreading machine. A processor is placed in a reliable execution mode (REM) to detect possible errors during execution of a software application. Only two threads may be configured to operat... | 12/20/2011 |
| 8024554 | Modifying an instruction stream using one or more bits to replace an instruction or to replace an instruction and to subsequently execute the replaced instruction A processor comprising fetch logic adapted to fetch instructions from memory and decode logic coupled to the fetch logic and adapted to decode the fetched instructions. If a bit in the decode logic is in a first state, a particular fetched instruction is skipped and... | 09/20/2011 |
| 8024555 | Condition code flag emulation for program code conversion An emulator allows subject code written for a subject processor having subject processor registers and condition code flags to run in a non-compatible computing environment. The emulator identifies and records parameters of instructions in the subject code that affe... | 09/20/2011 |
| 8010772 | Protected function calling Memory address space is divided into domains and instruction access control circuitry is used to detect when the memory address from which an instruction to be executed is fetched has crossed a domain boundary and changed and in such cases to conduct a check to ensu... | 08/30/2011 |
| 8010773 | Hardware constrained software execution Restricting execution by a computing device of instructions within an application program. The application program is modified such that execution of the selected instructions is dependent upon a corresponding expected state of one or more hardware components in the... | 08/30/2011 |
| 7984277 | System and method of instruction modification A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine lang... | 07/19/2011 |
| 7984276 | Method and system for altering processor execution of a group of instructions An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instru... | 07/19/2011 |
| 7979683 | Multiple simultaneous context architecture Graphics processing elements are capable of processing multiple contexts simultaneously, reducing the need to perform time consuming context switches compared with processing a single context at a time. Processing elements of a graphics processing pipeline may be co... | 07/12/2011 |
| 7895420 | System and method for eliminating common subexpressions in a linear system A method for reducing operations in a processing environment is provided that includes generating one or more binary representations, one or more of the binary representations being included in one or more linear equations that include one or more operations. The me... | 02/22/2011 |
| 7882336 | Employing a buffer to facilitate instruction execution Instruction execution is facilitated by employing a buffer to handle instructions having special circumstances. When such an instruction is to be executed, a pointer of the instruction is directed to the buffer. The instruction is executed from the buffer and then t... | 02/01/2011 |
| 7877582 | Multi-addressable register file A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments, are addressable with different instruction forms, e.g., scalar instruct... | 01/25/2011 |
| 7849295 | Data processing apparatus and data processing method including dividing data to be processed A data processing apparatus includes an operation processing unit and a data feature determining circuit. The operation processing unit is configured to sequentially perform preset operation processing on operation data in units of sub blocks to output an operation ... | 12/07/2010 |
| 7844803 | Configurable data processing device with bit reordering on inputs and outputs of configurable logic function blocks A data processing device has a configurable functional unit for executing an instruction according to a configurable function. The configurable functional unit has a plurality of independent configurable logic blocks for performing programmable logic operations to i... | 11/30/2010 |
| 7836282 | Method and apparatus for performing out of order instruction folding and retirement The illustrative embodiments described herein provide a computer implemented method, apparatus, and computer program product for increasing a number of instructions per clock cycle associated with a processor. The illustrative embodiments fold a plurality of non-seq... | 11/16/2010 |
| 7831813 | Uses of known good code for implementing processor architectural modifications In one embodiment, a processor comprises a programmable map and a circuit. The programmable map is configured to store data that identifies at least one instruction for which an architectural modification of an instruction set architecture implemented by the process... | 11/09/2010 |
| 7818550 | Method and apparatus for dynamically fusing instructions at execution time in a processor of an information handling system One embodiment of a processor includes a fetch stage, decoder stage, execution stage and completion stage. The execution stage includes a primary execution stage for handling low latency instructions and a secondary execution stage for handling higher latency instru... | 10/19/2010 |
| 7797517 | Trace optimization via fusing operations of a target architecture operation set Reference architecture instructions are translated into target architecture operations. Sequences of operations, in a predicted execution order in some embodiments, form traces. In some embodiments, a trace is based on a plurality of basic blocks. In some embodiment... | 09/14/2010 |
| 7757069 | Configuration steering for a reconfigurable superscalar processor A reconfigurable processor including a plurality of reconfigurable execution units, a memory, an instruction queue, a configuration selection unit, and a configuration loader. The memory stores a plurality of steering vector processing hardware configurations for co... | 07/13/2010 |
| 7725691 | Method and apparatus for accelerating processing of a non-sequential instruction stream on a processor with multiple compute units Accelerating processing of a non-sequential instruction stream on a processor with multiple compute units by broadcasting to a plurality of compute units a generic instruction stream derived from a sequence of instructions; the generic instruction stream including a... | 05/25/2010 |
| 7716458 | Reconfigurable integrated circuit, system development method and data processing method An integrated circuit includes a processor. An arithmetic logic circuit group includes a plurality of operation units and a connection channel connecting the operation units in a reconfigurable manner. Parameter-based dedicated hardware can change a process specific... | 05/11/2010 |
| 7711931 | Synchronized storage providing multiple synchronization semantics A shared resource access control system having a gating storage responsive to a plurality of controls with each of the controls derived from an instruction context identifying the shared resource, the gating storage including a plurality of sets of access method fun... | 05/04/2010 |
| 7707393 | Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a comput... | 04/27/2010 |
| 7698539 | System and method of instruction modification A method and system of instruction modification. A first machine language instruction, which may comprise a plurality of discrete instructions, is fetched. Responsive to a trigger pattern in the first machine language instruction, a segment of the first machine lang... | 04/13/2010 |
| 7624256 | System and method wherein conditional instructions unconditionally provide output A conditional instruction architected to receive one or more operands as inputs, to output to a target the result of an operation performed on the operands if a condition is satisfied, and to not provide an output if the condition is not satisfied, is executed so th... | 11/24/2009 |
| 7620800 | Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions Multi-adaptive processing systems and techniques for enhancing parallelism and performance of computational functions are disclosed which can be employed in a myriad of applications including multi-dimensional pipeline computations for seismic applications, search a... | 11/17/2009 |
| 7596680 | System and method for encoding and decoding architecture registers A system and method to extend the number of architecturally visible registers in a processor while preserving the number of bits of the instruction encoding. The system comprises: an indirection table that encodes register patterns for the registers used in an instr... | 09/29/2009 |
| 7590829 | Extension adapter A processor system. The processor system comprises a processor having a first set of instructions associated therewith. The processor system also comprises a programmable logic device and an extension adapter coupled to the processor and the programmable logic devic... | 09/15/2009 |
| 7587583 | Method and system for processing a “WIDE” opcode when it is not used as a prefix for an immediately following opcode Methods and systems are provided for the selective use of a Java WIDE opcode as a prefix as defined in the instruction set of the Java virtual machine or performing a task assigned to the Java WIDE opcode. A Java WIDE opcode is fetched, a determination is made as to... | 09/08/2009 |
| 7543135 | Processor and method for selectively processing instruction to be read using instruction code already in pipeline or already stored in prefetch buffer There is provided a processor including: an instruction pipeline pipeline-processing an instruction code; a comparison unit that compares an instruction code in the instruction pipeline or in an instruction prefetch buffer and an instruction code to be read next fro... | 06/02/2009 |
| 7533250 | Automatic operand load, modify and store A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if i... | 05/12/2009 |
| 7502918 | Method and system for data dependent performance increment and power reduction A method of dispatching instructions includes dispatching original instructions into an instruction buffer, including at least one operand, renaming the operand, selecting the original instructions from the instruction buffer, sending selected instructions with expl... | 03/10/2009 |
| 7487338 | Data processor for modifying and executing operation of instruction code according to the indication of other instruction code A MOD_SAT instruction indicating that a 16 bit saturation is to be carried out with respect to the operation of one of instructions executed in parallel is placed in the left container and an ADD instruction is placed in the right container. When the instruction dec... | 02/03/2009 |
| 7451297 | Computing system and method that determines current configuration dependent on operand input from another configuration A dataflow graph is split into sub-graphs referred to as configurations, each configuration comprising computational hardware containing elements that operate on operand sets. A configuration executes by consuming completed operand sets from a designated input tag s... | 11/11/2008 |
| 7434035 | Method and system for processing instructions in grouped and non-grouped modes An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instru... | 10/07/2008 |
| 7434004 | Prefetch prediction Predicting prefetch data sources for runahead execution triggering read operations eliminates the latency penalties of missing read operations that typically are not addressed by runahead execution mechanisms. Read operations that most likely trigger runahead execut... | 10/07/2008 |
| 7418575 | Long instruction word processing with instruction extensions A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of computational instructions and long instruction word instructions with ... | 08/26/2008 |
| 7418579 | Component with a dynamically reconfigurable architecture The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through interconnections so as to enable processing in pipeline or parallel mode ... | 08/26/2008 |
| 7415601 | Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an out... | 08/19/2008 |
