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"I hate what they've done to my child...I would never let my own children watch it. "
Vladimir Zworykin, television pioneer ; Talking about an invention in which he played a critical role.
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| Number | Title | Issue Date |
| 8181003 | Instruction set design, control and communication in programmable microprocessor cores and the like Improved instruction set and core design, control and communication for programmable microprocessors is disclosed, involving the strategy for replacing centralized program sequencing in present-day and prior art processors with a novel distributed program sequencing... | 05/15/2012 |
| 8171266 | Look-ahead load pre-fetch in a processor A method for look-ahead load pre-fetching that reduces the effects of instruction stalls caused by high latency instructions. Look-ahead load pre-fetching is accomplished by searching an instruction stream for load memory instructions while the instruction stream is... | 05/01/2012 |
| 8171267 | Method and apparatus for migrating task in multi-processor system A method and apparatus for migrating a task in a multi-processor system. The method includes examining whether a second process has been allocated to a second processor, the second process having a same instruction to execute as a first process and having different ... | 05/01/2012 |
| 8161271 | Store misaligned vector with permute Embodiments of the invention provide logic within the store data path between a processor and a memory array. The logic may be configured to misalign vector data as it is stored to memory. By misaligning vector data as it is stored to memory, memory bandwidth may be... | 04/17/2012 |
| 8161272 | Memory control circuit and integrated circuit including branch instruction detection and operation mode control of a memory The memory unit is compatible with a plurality of operation modes. The plurality of operation modes include the normal mode allowing access and the standby mode consuming a lower power than the normal mode. The branch detection section detects a branch instruction f... | 04/17/2012 |
| 8156314 | Incremental state updates A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The system and method are applicable to any processor in which multiple thread... | 04/10/2012 |
| 8131982 | Branch prediction instructions having mask values involving unloading and loading branch history data A method for branch prediction, the method comprising, receiving a load instruction including a first data location in a first memory area, retrieving data including a branch address and a target address from the first data location, and saving the data in a branch ... | 03/06/2012 |
| 8108658 | Data processing circuit wherein functional units share read ports A data processing circuit comprises a register file (14) having read ports and write ports. A plurality of functional units (21a-c), is coupled to receive operand data from a same combination of read ports. Each functional unit is coupled... | 01/31/2012 |
| 8108659 | Controlling access to memory resources shared among parallel synchronizable threads Thread synchronization techniques are used to control access to a memory resource (e.g., a counter) that is shared among multiple threads. Each thread has a unique identifier and threads are assigned to instances of the shared resource so that at least one instance ... | 01/31/2012 |
| 8108661 | Data processing apparatus and method of controlling the data processing apparatus Provided are a data processing apparatus and a method of controlling the data processing apparatus. The data processing apparatus may select a single stream processor from a plurality of stream processors based on stream processor status information, and input data ... | 01/31/2012 |
| 8108660 | Multiprocessor system and method of synchronization for multiprocessor system Each of processors has a barrier write register and a barrier read register. Each barrier write register is wired to each barrier read register by a dedicated wiring block. For example, a 1-bit barrier write register of a processor is connected, via the wiring block... | 01/31/2012 |
| 8103859 | Information processing apparatus, cache memory controlling apparatus, and memory access order assuring method According to an aspect of the embodiment, when data on a cache RAM is rewritten in a storage processing of one thread, an determination unit searches a fetch port which holds a request of another thread, checks whether a request exists whose processing is completed,... | 01/24/2012 |
| 8086827 | Mechanism for irrevocable transactions A method and apparatus for designating and handling irrevocable transaction is herein described. In response to detecting an irrevocable event, such as an I/O operation, a user-defined irrevocable designation, and a dynamic failure profile, a transaction is designat... | 12/27/2011 |
| 8078848 | Memory controller having front end and back end channels for modifying commands The present disclosure includes methods, devices, modules, and systems for modifying commands. One device embodiment includes a memory controller including a channel, wherein the channel includes a command queue configured to hold commands, and circuitry configured ... | 12/13/2011 |
| 8078847 | Detecting memory-hazard conflicts during vector processing A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addres... | 12/13/2011 |
| 8065506 | Application specific instruction set processor for digital radio processor receiving chain signal processing This invention is an application specific integrated processor to implement the complete fixed-rate DRX signal processing paths (FDRX) for a reconfigurable processor-based multi-mode 3G wireless application. This architecture is based on the baseline 16-bit RISC arc... | 11/22/2011 |
| 8060728 | Generating stop indicators during vector processing A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addres... | 11/15/2011 |
| 8060729 | Software based data flows addressing hardware block based processing requirements In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks having increased functionality. Each hardware block may be able to transfer a data packet to a particular hardware block based on the packet being processing. On... | 11/15/2011 |
| 8055885 | Data processing device for implementing instruction reuse, and digital data storage medium for storing a data processing program for implementing instruction reuse A method and apparatus is provided for significantly speeding-up program execution in a data processing device. The data processing device is provided with a specialized instruction region storage section comprising content addressable memory (CAM) and random access... | 11/08/2011 |
| 8046568 | Microprocessor with integrated high speed memory The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a comput... | 10/25/2011 |
| 8041928 | Information handling system with real and virtual load/store instruction issue queue An information handling system includes a processor that may perform issue queue virtual load/store instruction operations. The issue queue maintains load and store instructions with a real/virtual dependency flag. The issue queue provides storage resources for real... | 10/18/2011 |
| 8032735 | Load/move duplicate instructions for a processor A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register. ... | 10/04/2011 |
| 8024553 | Data exchange and communication between execution units in a parallel processor A method of operation within an integrated-circuit processing device having a plurality of execution lanes. Upon receiving an instruction to exchange data between the execution lanes, respective requests from the execution lanes are examined to determine a set of th... | 09/20/2011 |
| 8019977 | Generating predicate values during vector processing A method for performing parallel operations in a computer system when one or more memory hazards may be present, which may be implemented by a processor, is described. During operation, the processor receives instructions for detecting conflict between memory addres... | 09/13/2011 |
| 8019976 | Memory-hazard detection and avoidance instructions for vector processing A processor that is configured to perform parallel operations in a computer system where one or more memory hazards may be present is described. An instruction fetch unit within the processor is configured to fetch instructions for detecting one or more critical mem... | 09/13/2011 |
| 8019975 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose i... | 09/13/2011 |
| 8006075 | Dynamically allocated store queue for a multithreaded processor Systems and methods for storage of writes to memory corresponding to multiple threads. A processor comprises a store queue, wherein the queue dynamically allocates a current entry for a committed store instruction in which entries of the array may be allocated out o... | 08/23/2011 |
| 8006074 | Methods and apparatus for executing extended custom instructions Methods and apparatus are provided for efficiently executing extended custom instructions on a programmable chip. Components of a processor core such as arithmetic logic units, program sequencer units, and address generation units are integrated with customizable lo... | 08/23/2011 |
| 7991981 | Completion of asynchronous memory move in the presence of a barrier operation A method within a data processing system by which a processor executes an asynchronous memory move (AMM) store (ST) instruction to complete a corresponding AMM operation in parallel with an ongoing (not yet completed), previously issued barrier operation. The proces... | 08/02/2011 |
| 7991982 | Microcomputer and encoding system for executing peripheral function instructions A microcomputer that can process plural tasks time-divisionally and in parallel, wherein one of a plural programs described by one of the tasks is described as a looped specific task in which the increment of program addresses is fixed, a program counter is usable a... | 08/02/2011 |
| 7984274 | Partial load/store forward prediction In one embodiment, a processor comprises a prediction circuit and another circuit coupled to the prediction circuit. The prediction circuit is configured to predict whether or not a first load instruction will experience a partial store to load forward (PSTLF) event... | 07/19/2011 |
| 7984275 | Computer configuration virtual topology discovery and instruction therefore In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration f... | 07/19/2011 |
| 7984273 | System and method for using a mask register to track progress of gathering elements from memory A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate th... | 07/19/2011 |
| 7979681 | System and method of selectively accessing a register file In a particular embodiment, a method is disclosed that includes identifying a first block of bits within a result to be written to a destination register by an execution unit. The result includes a plurality of bits having the first block of bits and a second block ... | 07/12/2011 |
| 7979682 | Method and system for preventing livelock due to competing updates of prediction information A system to prevent livelock. An outcome of an event is predicted to form an event outcome prediction. The event outcome prediction is compared with a correct value for a datum to be accessed. An instruction is appended with a real event outcome when the outcome of ... | 07/12/2011 |
| 7975130 | Method and system for early instruction text based operand store compare reject avoidance A method and system for early instruction text based operand store compare avoidance in a processor are provided. The system includes a processor pipeline for processing instruction text in an instruction stream, where the instruction text includes operand address i... | 07/05/2011 |
| 7971038 | Asynchronous ripple pipeline An asynchronous ripple pipeline has a plurality of stages, each with a controller (18) and a register (16). The controller has a register control output (21), and a combined acknowledgement and request output (20), together with a request... | 06/28/2011 |
| 7971039 | Conditional memory ordering A system for conditional memory ordering implemented in a multiprocessor environment. A conditional memory ordering instruction executes locally using a release vector containing release numbers for each processor in the system. The instruction first determines whet... | 06/28/2011 |
| 7962730 | Replaying memory operation assigned a load/store buffer entry occupied by store operation processed beyond exception reporting stage and retired from scheduler In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at ... | 06/14/2011 |
| 7958341 | Processing stream instruction in IC of mesh connected matrix of processors containing pipeline coupled switch transferring messages over consecutive cycles from one link to another link or memory In some embodiments, each matrix processor in a matrix of mesh-interconnected matrix processors includes an instruction processing pipeline, and a hardware data switch capable of streaming data to/from one or more inter-processor matrix links and/or a matrix process... | 06/07/2011 |
