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| Number | Title | Issue Date |
| 8161270 | Packet data modification processor A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in respon... | 04/17/2012 |
| 8145885 | Apparatus for randomizing instruction thread interleaving in a multi-thread processor A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency ... | 03/27/2012 |
| 8127117 | Method and system to combine corresponding half word units from multiple register units within a microprocessor A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined dispa... | 02/28/2012 |
| 7895419 | Rotate then operate on selected bits facility and instructions therefore A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second r... | 02/22/2011 |
| 7818549 | Event driven digital signal processor with time constraints The present invention relates to an event driven digital signal processor 1 comprising: a central arithmetical unit 5, a register 4, a controller 3, an instruction memory 2, and input/output devices. The instruction memory 2... | 10/19/2010 |
| 7685408 | Methods and apparatus for extracting bits of a source register based on a mask and right justifying the bits into a target register Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target re... | 03/23/2010 |
| 7634638 | Instruction encoding for system register bit set and clear An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kern... | 12/15/2009 |
| 7600100 | Instruction encoding for system register bit set and clear An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates the instructions are to be executed in privileged (kernel) state only, and are... | 10/06/2009 |
| 7565515 | Method and software for store multiplex operation A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field ... | 07/21/2009 |
| 7555636 | Atomically updating 64 bit fields in the 32 bit AIX kernel A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-... | 06/30/2009 |
| 7526635 | Programmable processor and system for store multiplex operation A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspo... | 04/28/2009 |
| 7480787 | Method and structure for pipelining of SIMD conditional moves A mask is first generated in a general-purpose integer register. The mask is generated by executing a single instruction multiple data (SIMD) instruction on a plurality of operands stored in a plurality of registers and by writing the result to the general-purpose i... | 01/20/2009 |
| 7437541 | Atomically updating 64 bit fields in the 32 bit AIX kernel A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-... | 10/14/2008 |
| 7404068 | Single operation per-bit memory access Mechanisms for performing per-bit operations in system memory in a single operation thereby obviating the need for semaphore mechanisms when performing per-bit operations. A processor accesses an instruction that identifies the specific bit of system memory that is ... | 07/22/2008 |
| 7401204 | Parallel Processor efficiently executing variable instruction word A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units pe... | 07/15/2008 |
| 7401208 | Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency ... | 07/15/2008 |
| 7373463 | Antifraud method and circuit for an integrated circuit register containing data obtained from secret quantities An integrated circuit and an antifraud method implementing at least one operation involving at least one secret quantity, and functionally including upstream and downstream of the operator at least one source register and at least one destination register, respectiv... | 05/13/2008 |
| 7370184 | Shifter for alignment with bit formatter gating bits from shifted operand, shifted carry operand and most significant bit An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby generating a shifted operand. The register is coupled to the shift post pro... | 05/06/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7353501 | Generic wrapper scheme A method instruments a function in an executable file so that the instrumented function calls a generic preprocessor prior to execution of the body of the function. After the preprocessor modifies the original function's incoming parameters, the body of the function... | 04/01/2008 |
| 7350058 | Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination va... | 03/25/2008 |
| 7340635 | Register-based de-skew system and method for a source synchronous receiver A register-based de-skew system and method for a source synchronous receiver circuit domain. In one embodiment, a de-skew strobe generator operates responsive to at least one incoming strobe signal in order to generate a plurality of one-hot de-skew strobe signals. ... | 03/04/2008 |
| 7330937 | Management of stack-based memory usage in a processor A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as eith... | 02/12/2008 |
| 7318014 | Bit accurate hardware simulation in system level simulators A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the system level simulator. These simulations take advantage of the comp... | 01/08/2008 |
| 7302511 | Chipset support for managing hardware interrupts in a virtual machine system In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a dist... | 11/27/2007 |
| 7290122 | Dataflow graph compression for power reduction in a vector processor A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each ordered field containing an instruction for an element of the processor. T... | 10/30/2007 |
| 7290289 | Processor with several calculating units A processor comprises a first calculating unit, a second calculating unit and a control means for controlling the two calculating units, such that they selectively operate in a high security mode of operation processing complementary data or in a parallel mode of op... | 10/30/2007 |
| 7281123 | Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second... | 10/09/2007 |
| 7278011 | Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive number of outstanding instructions. Each entry may be configured to store... | 10/02/2007 |
| 7278030 | Virtualization system for computers having multiple protection mechanisms In a virtual computer system, the invention virtualizes a primary protection mechanism, which restricts memory accesses based on the type of access attempted and a current hardware privilege level, using a secondary protection mechanism, which is independent of the ... | 10/02/2007 |
| 7275147 | Method and apparatus for data alignment and parsing in SIMD computer architecture Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a shift value, preferably as parameters of the instruction. A first and... | 09/25/2007 |
| 7275149 | System and method for evaluating and efficiently executing conditional instructions A system, circuit, and method are presented for evaluating conditional execution instructions. The system, circuit, and method are adapted to receive an identification instruction comprising the size and the condition of execution of a block of conditional execution... | 09/25/2007 |
| 7269720 | Dynamically controlling execution of operations within a multi-operation instruction Techniques are described for dynamically controlling the execution of operations within a multi-operation instruction, such as a very long instruction word (VLIW). A programmable processor fetches and executes a first instruction having an operation mask. Based on t... | 09/11/2007 |
| 7254699 | Aligning load/store data using rotate, mask, zero/sign-extend and or operation The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is disclosed for loading unaligned data stored in several memory locations, incl... | 08/07/2007 |
| 7249224 | Methods and apparatus for providing early responses from a remote data cache According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for allowing a variety of transactions to complete locally are implemented by providing r... | 07/24/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7237097 | Partial bitwise permutations Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and... | 06/26/2007 |
| 7231510 | Pipelined multiply-accumulate unit and out-of-order completion logic for a superscalar digital signal processor and method of operation thereof A mechanism for, and method of, processing multiply-accumulate instructions with out-of-order completion in a pipeline, for use in a processor having an at least four-wide instruction issue architecture, and a digital signal processor (DSP) incorporating the mechani... | 06/12/2007 |
| 7228401 | Interfacing a processor to a coprocessor in which the processor selectively broadcasts to or selectively alters an execution mode of the coprocessor The present invention relates generally to interfacing a processor with at least one coprocessor. One embodiment relates to a processor having a set of broadcast specifiers which it uses to selectively broadcast an operand that is being written to a register within ... | 06/05/2007 |
| 7219213 | Flag bits evaluation for multiple vector SIMD channels execution According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by th... | 05/15/2007 |
