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| Number | Title | Issue Date |
| 8024552 | Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift... | 09/20/2011 |
| 7783627 | Database retrieval with a unique key search on a parallel computer system An apparatus and method retrieves a database record from an in-memory database of a parallel computer system using a unique key. The parallel computer system performs a simultaneous search on each node of the computer system using the unique key and then utilizes a ... | 08/24/2010 |
| 7761695 | Programmable data processor for a variable length encoder/decoder A data processing circuit has a programmable processor (12a, b) with an instruction set that comprises an new type of instruction. This instruction has a first operand that refers to a string of bits, and a second operand that refers to a position in that str... | 07/20/2010 |
| 7752424 | Null value checking instruction A processor 2 is provided with the ability to execute program instructions in the form of Java bytecodes including a dedicated null checking instruction. The null checking instruction reads the top of stack value, compares this with a null value and jumps to ... | 07/06/2010 |
| 7721072 | Information processing method and apparatus, recording medium, and program An information processing method includes generating a state transition diagram based on state transition information; displaying the state transition diagram; manipulating the displayed state transition diagram; updating the state transition information in accordan... | 05/18/2010 |
| 7610472 | Performing variable and/or bitwise shift operation for a shift instruction that does not provide a variable or bitwise shift option Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift... | 10/27/2009 |
| 7594099 | Processor executing SIMD instructions A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC | 09/22/2009 |
| 7565514 | Parallel condition code generation for SIMD operations A processing system and method performs data processing operations in response to a single data processing instruction. At least two registers store data. First control circuitry compares data in respective corresponding fields of the at least two registers to creat... | 07/21/2009 |
| 7519795 | Method and system for performing permutations with bit permutation instructions The present invention provides permutation instructions which can be used in software executed in a programmable processor for solving permutation problems in cryptography, multimedia and other applications. PPERM and PPERM3R instructions are defined to perform perm... | 04/14/2009 |
| 7406592 | Method, system, and apparatus for efficient evaluation of boolean expressions Methods, systems, and computer-readable media are provided for efficiently evaluation Boolean expressions. According to the method, the Boolean expression is expressed using pre-fix notation. Each element in the pre-fix expression is then parsed. For each first oper... | 07/29/2008 |
| 7370180 | Bit field extraction with sign or zero extend A method of controlling data processing logic which causes a data value to be rotated by a number of bits in order to generate a rotated data value; a number of least significant bits of the rotated data value are masked with other bits of said rotated data value no... | 05/06/2008 |
| 7360066 | Boolean processor A processor including a Boolean logic unit, wherein the Boolean logic unit is operable for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, a plurality of input/output interfaces, wherein the plurality of input/outpu... | 04/15/2008 |
| 7360069 | Systems and methods for executing across at least one memory barrier employing speculative fills Multi-processor systems and methods are provided. One embodiment relates to a multi-processor system that may comprise a processor having a processor pipeline that executes program instructions across at least one memory barrier with data from speculative data fills... | 04/15/2008 |
| 7353371 | Circuit to extract nonadjacent bits from data packets A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination data fields in a result packet governed by a field locator packet. I... | 04/01/2008 |
| 7353367 | System and software for catenated group shift instruction A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the e... | 04/01/2008 |
| 7353488 | Flow definition language for designing integrated circuit implementation flows An instance of a flow definition language for designing an integrated circuit implementation flow. The instance of the flow definition language includes a hierarchical collection of stages for a physical chip design. Relational constraints define the execution order... | 04/01/2008 |
| 7349494 | Method and apparatus for receiving and deshuffling shuffled data in a high-rate packet data telecommunication system A method and apparatus for deshuffling received shuffled data in a communication system supporting multi-level modulation. A transmitter encodes information bits and shuffles code symbols so that systematic symbols having a relatively high priority are disposed at h... | 03/25/2008 |
| 7334111 | Method and related device for use in decoding executable code The invention provides for a method and related device and control program for use in decoding executable code in a processing system, for example run-time operating system, including bit-shuffling code at run-time, and including the steps of dividing the code into ... | 02/19/2008 |
| 7330937 | Management of stack-based memory usage in a processor A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as eith... | 02/12/2008 |
| 7320065 | Multithread embedded processor with input/output capability An embedded processor system having a single-chip embedded microprocessor with analog and digital electrical interfaces to external systems. A novel processor core uses pipelined execution of multiple independent or dependent concurrent threads, together with superv... | 01/15/2008 |
| 7315261 | Method for converting data from pixel format to bitplane format This invention efficiently converts normal pixel data into bit plane data. A sequence of pack, bitwise shuffle, masking, rotate and merging operations transform tile from pixel form to bit plane form. This enables downstream algorithms to read only the data for the ... | 01/01/2008 |
| 7315936 | Enhanced boolean processor A set of processors, co-processors and processor cores having a Boolean logic unit, wherein the Boolean logic unit is operable, respectively, for performing the short-circuit evaluation of Conjunctive Normal Form Boolean expressions/operations, Disjunctive Normal Fo... | 01/01/2008 |
| 7315937 | Microprocessor instructions for efficient bit stream extractions A method of extracting bits of a bit stream including retrieving bits from the bit stream into an accumulator, specifying a size value specifying a number of bits to extract, storing a position value into a control register, and executing a bit extraction instructio... | 01/01/2008 |
| 7302553 | Apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a prese... | 11/27/2007 |
| 7299282 | State processor for pattern matching in a network monitor device A processor for processing contents of packets passing through a connection point on a computer network. The processor includes a searching apparatus having one or more comparators for searching for a reference string in the contents of a packet, and processes conte... | 11/20/2007 |
| 7290106 | Method for processor to use locking cache as part of system memory The present invention provides a method for a processor to write data to a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory until it is loaded for use. Data remains in the locki... | 10/30/2007 |
| 7290289 | Processor with several calculating units A processor comprises a first calculating unit, a second calculating unit and a control means for controlling the two calculating units, such that they selectively operate in a high security mode of operation processing complementary data or in a parallel mode of op... | 10/30/2007 |
| 7290107 | Direct deposit using locking cache The present invention provides a method of storing data transferred from an I/O device, a network, or a disk into a portion of a cache or other fast memory, without also writing it to main memory. Further, the data is “locked” into the cache or other fast memory... | 10/30/2007 |
| 7281140 | Digital throttle for multiple operating points A processor includes a digital throttle to monitor the activity of various units of the processor's instruction execution pipeline. The monitored activity is scaled according to the current operating point of the processor and a power state is determined from the sc... | 10/09/2007 |
| 7280492 | Videoconferencing system A multicasting conferencing system is described wherein permanently or temporarily assigned addressing may be used. When permanently assigned multicast addressing is used, several channel parameters are assigned to a multicast session, and any terminals desiring to ... | 10/09/2007 |
| 7272622 | Method and apparatus for parallel shift right merge of data A method for a parallel shift right merge of data. The method of one embodiment comprises receiving a shift count of M. A first operand having a first set of L data elements is shifted left by ‘L−M’ data elements. A second operand having a second set of L data... | 09/18/2007 |
| 7260708 | Programmable processor and method for partitioned group shift A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the e... | 08/21/2007 |
| 7254696 | Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit th... | 08/07/2007 |
| 7246187 | Method and apparatus for controlling exclusive access to a shared resource in a data storage system A method for controlling exclusive access to a resource shared by multiple processors in a data storage system includes providing a system lock procedure to permit a processor to obtain a lock on the shared resource preventing other processors from accessing the sha... | 07/17/2007 |
| 7243372 | Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection A processor has an architecture that provides the processing speed advantages of the Harvard architecture, but does not require two separate external memories in order to expand both data memory and program instruction memory. The processor has separate program memo... | 07/10/2007 |
| 7237055 | System, apparatus and method for data path routing configurable to perform dynamic bit permutations A system, apparatus and a method for routing data over fewer switches and interconnections among reconfigurable logic elements, and for adapting routing resources to dynamically perform complex bit-level permutations, such as shifting and bit reversal operations. In... | 06/26/2007 |
| 7237097 | Partial bitwise permutations Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier, a previous partial value source, a destination subset specifier, and... | 06/26/2007 |
| 7231414 | Apparatus and method for performing addition of PKG recoded numbers An apparatus and method provide an apparatus and method for performing the addition of a PKG recoded number, to reduce noise production and power consumption. In particular, the apparatus is accomplished by a circuitry configured to receive at least two values, a fi... | 06/12/2007 |
| 7228266 | Instruction processor emulator having separate operand and op-code interfaces Techniques are described for emulating an instruction processor for use during the development of a computer system. Specifically, the techniques describe an emulated instruction processor that accurately and efficiently emulates an instruction processor having sepa... | 06/05/2007 |
| 7219214 | Data processing apparatus and method for moving data elements between a chosen lane of parallel processing in registers and a structure within memory A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in par... | 05/15/2007 |
