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| Number | Title | Issue Date |
| 8131981 | SIMD processor performing fractional multiply operation with saturation history data processing to generate condition code flags A data processing system, apparatus and method for performing fractional multiply operations is disclosed. The system includes a memory that stores instructions for SIMD operations and a processing core. The processing core includes registers that store operands for... | 03/06/2012 |
| 8117426 | System and apparatus for group floating-point arithmetic operations Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data ... | 02/14/2012 |
| 8108657 | Handling floating point operations A computing system capable of handling floating point operations during program code conversion is described, comprising a processor including a floating point unit and an integer unit. The computing system further comprises a translator unit arranged to receive sub... | 01/31/2012 |
| 8103858 | Efficient parallel floating point exception handling in a processor Methods and apparatus are disclosed for handling floating point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. In one embodiment a numerical exception is identified for a SIMD floating point operation and SIMD micro-ope... | 01/24/2012 |
| 8074058 | Providing extended precision in SIMD vector arithmetic operations The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. ... | 12/06/2011 |
| 8028153 | Data dependent instruction decode A circuit arrangement and method support data dependent instruction decoding, whereby instructions are decoded, in part, using decode data that is stored in operand registers identified by such instructions. An instruction may include an opcode and at least one oper... | 09/27/2011 |
| 7949858 | Multifunction hexadecimal instruction form system and program product A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructi... | 05/24/2011 |
| 7945766 | Conditional execution of floating point store instruction by simultaneously reading condition code and store data from multi-port register file A processor capable of executing conditional store instructions without being limited by the number of condition codes is provided. Condition data is stored in floating-point registers, and an operation unit executes a conditional floating-point store instruction of... | 05/17/2011 |
| 7904699 | Processing unit incorporating instruction-based persistent vector multiplexer control Persistent vector multiplexer control is used in a vector-based execution unit to control the shuffling of words in operand vectors processed by the execution unit. In addition, a persistent swizzle instruction is defined in an instruction set for the vector-based e... | 03/08/2011 |
| 7904700 | Processing unit incorporating special purpose register for use with instruction-based persistent vector multiplexer control A software-accessible special purpose register is architected into a processing unit in order to implement persistent vector multiplexer control of a vector-based execution unit. A persistent swizzle instruction is defined in an instruction set for the vector-based ... | 03/08/2011 |
| 7900025 | Floating point only SIMD instruction set architecture including compare, select, Boolean, and alignment operations Mechanisms for implementing a floating point only single instruction multiple data instruction set architecture are provided. A processor is provided that comprises an issue unit, an execution unit coupled to the issue unit, and a vector register file coupled to the... | 03/01/2011 |
| 7895418 | Operand queue for use in a floating point unit to reduce read-after-write latency and method operation There is disclosed an operand queue for use in a floating point unit. The floating point unit comprises floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions ... | 02/22/2011 |
| 7818548 | Method and software for group data operations Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple d... | 10/19/2010 |
| 7765386 | Scalable parallel pipeline floating-point unit for vector processing An embodiment of the present invention is a technique to perform floating-point operations for vector processing. An input queue captures a plurality of vector inputs. A scheduler dispatches the vector inputs. A plurality of floating-point (FP) pipelines generates F... | 07/27/2010 |
| 7730287 | Method and software for group floating-point arithmetic operations Methods and software are presented for processing data in a programmable processor, involving (a) decoding instructions for execution using an execution unit operable to execute instructions by partitioning data stored in registers in a register file into multiple d... | 06/01/2010 |
| 7660973 | System and apparatus for group data operations Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data ... | 02/09/2010 |
| 7660972 | Method and software for partitioned floating-point multiply-add operation A method and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply t... | 02/09/2010 |
| 7574584 | Splitting execution of a floating-point add instruction between an integer pipeline for performing mantissa addition and a hardware state machine In some embodiments, a processor includes fetch logic that fetches instructions, an integer pipeline, and a hardware state machine that is separate from and interacts with the integer pipeline. The instruction is executed partly in the integer pipeline according to ... | 08/11/2009 |
| 7565513 | Processor with power saving reconfigurable floating point unit decoding an instruction to single full bit operation or multiple reduced bit operations A technique of operating a processor includes determining whether a floating point unit (FPU) of the processor is to operate in a full-bit mode or a reduced-bit mode. An instruction is fetched and the instruction is decoded into a single operation, when the full-bit... | 07/21/2009 |
| 7558947 | Method and apparatus for computing vector absolute differences Methods and apparatuses for computing an absolute difference of two vectors of numbers. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a single instruction includes: receiving a first plurality of numbers and a se... | 07/07/2009 |
| 7546443 | Providing extended precision in SIMD vector arithmetic operations The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. ... | 06/09/2009 |
| 7516307 | Processor for computing a packed sum of absolute differences and packed multiply-add A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to one embodiment, a processor includes a decode unit to decode a packed s... | 04/07/2009 |
| 7516308 | Processor for performing group floating-point operations A system and method expands a source operand to a width greater than that of a general purpose register or a data path. Operands are provided substantially larger than the data path width of a processor. The general purpose register specifies a memory address from w... | 04/07/2009 |
| 7457941 | Vector processing system A vector processing system for executing vector instructions, each instruction defining multiple pairs of values, an operation to be executed on each of said value pairs and a scalar modifier, the vector processing system comprising a plurality of parallel processin... | 11/25/2008 |
| 7437540 | Complex domain floating point VLIW DSP with data/program bus multiplexer and microprocessor interface A system for digital signal processing, configured as a system on chip (SoC), combines a microprocessor core and digital signal processor (DSP) core with floating-point data processing capability. The DSP core can perform operations on floating-point data in a compl... | 10/14/2008 |
| 7406589 | Processor having efficient function estimate instructions High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instr... | 07/29/2008 |
| 7395414 | Dynamic recalculation of resource vector at issue queue for steering of dependent instructions A method and apparatus for steering instructions dynamically, at issue time, so as to maximize the efficiency of use of execution units being shared by multiple threads being processed by an SMT processor. Resource vectors are used at issue time to redirect instruct... | 07/01/2008 |
| 7373489 | Apparatus and method for floating-point exception prediction and recovery An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction... | 05/13/2008 |
| 7373488 | Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a saturating operation, a first source having packed data elements and a seco... | 05/13/2008 |
| 7366749 | Floating point adder with embedded status information A system for providing a floating point sum includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and data ... | 04/29/2008 |
| 7366873 | Indirectly addressed vector load-operate-store method and apparatus A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 04/29/2008 |
| 7363337 | Floating point divider with embedded status information A system for providing floating point division includes an analyzer circuit configured to determine a first status of a first floating point operand and a second status of a second floating point operand based upon data within the first floating point operand and da... | 04/22/2008 |
| 7363478 | Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data consists of two vectors, which constitute the operands for a permute instruc... | 04/22/2008 |
| 7363471 | Apparatus, system, and method of dynamic binary translation supporting a denormal input handling mechanism A method may translate a set of source instructions into a set of target instructions, execute the set of target instructions, and unmask a denormal input control bit if the set of source instructions uses a denormal input handling mechanism. A method may detect at ... | 04/22/2008 |
| 7363475 | Managing registers in a processor to emulate a portion of a stack The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the top portion of the stack. Data is managed in these registers by managi... | 04/22/2008 |
| 7360220 | Methods and apparatus for multi-threading using differently coded software segments to perform an algorithm Methods and apparatus for multi-threading on a simultaneous multi-threading processor are provided. The methods and apparatus described herein increase computational throughput by launching two or more computational threads to perform the same algorithm using two di... | 04/15/2008 |
| 7356676 | Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the coprocessor and a coprocessor identification field for identifying a copr... | 04/08/2008 |
| 7353364 | Apparatus and method for sharing a functional unit execution resource among a plurality of functional units An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to execute instructions issued from the instruction fetch logic and to ... | 04/01/2008 |
| 7353503 | Efficient dead code elimination Disclosed is a method for eliminating dead code from a computer program using an operands graph generated from a flow graph of a computer program. In one embodiment of the present invention, the operands graph is traversed for any unused operands. Upon detection of ... | 04/01/2008 |
| 7350057 | Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an ins... | 03/25/2008 |
