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| Number | Title | Issue Date |
| 8190860 | Result forwarding to dependent instruction in pipelined processor with mode selectable execution in E1 or E2 of pipelined operational stages A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a secon... | 05/29/2012 |
| 8117425 | Multithread processor and method of synchronization operations among threads to be used in same The Thread Data Base 1 holds a thread identifier to uniquely identify a thread in the system. The Check means 3 lets, when no thread being a target exist in the same processor, a trap (TRAP) 10 occur. The Issue means 2, when a thread bein... | 02/14/2012 |
| 8099583 | Method of and apparatus and architecture for real time signal processing by switch-controlled programmable processor configuring and flexible pipeline and parallel processing A new signal processor technique and apparatus combining microprocessor technology with switch fabric telecommunication technology to achieve a programmable processor architecture wherein the processor and the connections among its functional blocks are configured b... | 01/17/2012 |
| 8078846 | Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated A conditional move instruction implemented in a processor by forming and processing two decoded instructions, and applications thereof. In an embodiment, the conditional move instruction specifies a first source operand, a second source operand, and a third operand ... | 12/13/2011 |
| 8065505 | Stall-free pipelined cache for statically scheduled and dispatched execution This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specificatio... | 11/22/2011 |
| 8055884 | Method and apparatus for augmenting a pipeline with a bubble-removal circuit One embodiment of the present invention provides a system for augmenting a pipeline with a bubble-removal circuit. During operation, the system generates a bubble-removal circuit which determines a clock-enable signal based at least on whether an upstream register h... | 11/08/2011 |
| 8037287 | Error recovery following speculative execution with an instruction processing pipeline An instruction processing pipeline 6 is provided. This has error detection and error recovery circuitry 20 associated with one or more of the pipeline stages. If an error is detected within a signal value within that pipeline stage, then it can be repa... | 10/11/2011 |
| 8028151 | Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructio... | 09/27/2011 |
| 8006072 | Reducing data hazards in pipelined processors to provide high processor utilization A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions... | 08/23/2011 |
| 7958340 | Monitoring software pipeline performance on a network on chip Software pipelining on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controlle... | 06/07/2011 |
| 7945765 | Method and structure for asynchronous skip-ahead in synchronous pipelines An electronic apparatus includes a plurality of stages serially interconnected as a pipeline to perform sequential processings on input operands. A shortening circuit associated with at least one stage of the pipeline recognizes when one or more of input operands fo... | 05/17/2011 |
| 7877580 | Branch lookahead prefetch for microprocessors A method of handling program instructions in a microprocessor which reduces delays associated with mispredicted branch instructions, by detecting the occurrence of a stall condition during execution of the program instructions, speculatively executing one or more pe... | 01/25/2011 |
| 7861066 | Mechanism for predicting and suppressing instruction replay in a processor A mechanism for suppressing instruction replay includes a processor having one or more execution units and a scheduler that issue instruction operations for execution by the one or more execution units. The scheduler may also cause instruction operations that are de... | 12/28/2010 |
| 7818544 | Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed... | 10/19/2010 |
| 7814300 | Configurable pipeline to process an operation at alternate pipeline stages depending on ECC/parity protection mode of memory access A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a secon... | 10/12/2010 |
| 7711930 | Apparatus and method for decreasing the latency between instruction cache and a pipeline processor A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an inter... | 05/04/2010 |
| 7689813 | Method and apparatus for enforcing membar instruction semantics in an execute-ahead processor Embodiments of the present invention provide a system that facilitates executing a memory barrier (membar) instruction in an execute-ahead processor, wherein the membar instruction forces buffered loads and stores to complete before allowing a following instruction ... | 03/30/2010 |
| 7676656 | Minimizing unscheduled D-cache miss pipeline stalls in a cascaded delayed execution pipeline A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more ex... | 03/09/2010 |
| 7653807 | Removing a pipeline bubble by blocking clock signal to downstream stage when downstream stage contains invalid data One embodiment of the present invention provides a system that removes a bubble from a pipeline. During operation, the system first detects a stall in the pipeline. The system next determines whether a first register contains invalid data, which is associated with a... | 01/26/2010 |
| 7620799 | Using a modified value GPR to enhance lookahead prefetch Mechanisms to identify and speculatively execute future instructions during a stall condition are provided. In speculative mode, instruction operands may be invalid due to a number of reasons. Dependency and dirty bits are tracked and used to determine which specula... | 11/17/2009 |
| 7516306 | Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies The present invention broadly contemplates braids and fibers, high-level programming constructs which facilitate the creation of programs that are partially ordered, to address the continuing trend of ever-increasing processor speeds and attendant increases in memor... | 04/07/2009 |
| 7475227 | Method of stalling one or more stages in an interlocked synchronous pipeline A method of operating an integrated circuit including a pipeline and a method of stalling stages in the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stag... | 01/06/2009 |
| 7472259 | Multi-cycle instructions In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall signal to stall the multi-cycle instruction within one of the stages of th... | 12/30/2008 |
| 7454600 | Method and apparatus for assigning thread priority in a processor or the like In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread precedence counter. To further augment, the effectiveness of the thread precedence counters, starting count... | 11/18/2008 |
| 7447879 | Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache miss A method and apparatus for minimizing unscheduled D-cache miss pipeline stalls is provided. In one embodiment, execution of an instruction in a processor is scheduled. The processor may have at least one cascaded delayed execution pipeline unit having two or more ex... | 11/04/2008 |
| 7444498 | Load lookahead prefetch for microprocessors The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the m... | 10/28/2008 |
| 7441245 | Phasing for a multi-threaded network processor A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divi... | 10/21/2008 |
| 7441101 | Thread-aware instruction fetching in a multithreaded embedded processor The present invention provides a multithreaded processor, such as a network processor, that fetches instructions in a pipeline stage based on feedback signals from later stages. The multithreaded processor comprises a pipeline with an instruction unit in the early s... | 10/21/2008 |
| 7437539 | Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline An issue unit for placing a processor into a gradual slow down mode of operation is provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slow... | 10/14/2008 |
| 7434033 | Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline Mechanisms for placing a processor into a gradual slow down mode of operation are provided. The gradual slow down mode of operation comprises a plurality of stages of slow down operation of an issue unit in a processor in which the issuance of instructions is slowed... | 10/07/2008 |
| 7421567 | Using a modified value GPR to enhance lookahead prefetch The present invention allows a microprocessor to identify and speculatively execute future instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the microp... | 09/02/2008 |
| 7421566 | Implementing instruction set architectures with non-contiguous register file specifiers There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction ... | 09/02/2008 |
| 7418625 | Deadlock detection and recovery logic for flow control based data path design Certain embodiments of the invention may be found in a method and system for handling deadlock conditions in a data processing system. Aspects of the method may comprise identifying a potential deadlock state in a distribute and merge data processing system. An actu... | 08/26/2008 |
| 7406588 | Dynamically reconfigurable stages pipelined datapath with data valid signal controlled multiplexer A pipelined datapath with dynamically reconfigurable pipeline stages is provided, having a pipeline controller which generates clock signals and selects signals based on a system clock and a valid data signal to control each of the registers and each of the multiple... | 07/29/2008 |
| 7404067 | Method and apparatus for efficient utilization for prescient instruction prefetch Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculati... | 07/22/2008 |
| 7401211 | Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor In a multi-threaded processor, a long latency data dependent thread is flushed from the execution pipelines. Once the stalled thread is flushed, the non-stalling threads in the pipeline can continue their execution. Several resources are used to reduce this unwanted... | 07/15/2008 |
| 7398358 | Method and apparatus for high performance branching in pipelined microsystems A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates delays caused by branch instructions, especially data-dependent unpredictable branches. In pipelined and mult... | 07/08/2008 |
| 7373489 | Apparatus and method for floating-point exception prediction and recovery An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction... | 05/13/2008 |
| 7373484 | Controlling writes to non-renamed register space in an out-of-order execution microprocessor A method of controlling write operations to a non-renamed register space includes receiving a write operation to a given register within the non-renamed register space. The method also includes determining whether a pending write operation to the given register exis... | 05/13/2008 |
| 7373463 | Antifraud method and circuit for an integrated circuit register containing data obtained from secret quantities An integrated circuit and an antifraud method implementing at least one operation involving at least one secret quantity, and functionally including upstream and downstream of the operator at least one source register and at least one destination register, respectiv... | 05/13/2008 |
