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| Number | Title | Issue Date |
| 8190859 | Critical section detection and prediction mechanism for hardware lock elision A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock instruction is detected with detection logic, which potentially resides in decode logic. A lock instruction entry... | 05/29/2012 |
| 8181001 | Conditional data-dependency resolution in vector processors Described is a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of condition... | 05/15/2012 |
| 8176299 | Generating stop indicators based on conditional data dependency in vector processors Described is a method for performing parallel operations in a computer system when one or more conditional dependencies may be present, where a given conditional dependency includes a dependency associated with at least two data elements based on a pair of condition... | 05/08/2012 |
| 8171263 | Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions A parallel data processing apparatus using a SIMD array of processing elements is disclosed. The apparatus makes use of a register in order to control issuance of instructions to the processing elements in the array. ... | 05/01/2012 |
| 8171262 | Method and apparatus for clearing hazards using jump instructions A method and apparatus for overlaying hazard clearing with a jump instruction within a pipeline microprocessor is described. The apparatus includes hazard logic to detect when a jump instruction specifies that hazards are to be cleared as part of a jump operation. I... | 05/01/2012 |
| 8171264 | Control sub-unit and control main unit A sub-unit judges whether an instruction received from an external unit is executable. If the instruction is judged to be executable, the sub-unit executes it. If, on the other hand, the instruction is judged to be unexecutable, the sub-unit notifies the external un... | 05/01/2012 |
| 8166281 | Implementing instruction set architectures with non-contiguous register file specifiers There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction ... | 04/24/2012 |
| 8135942 | System and method for double-issue instructions using a dependency matrix and a side issue queue A method receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method s... | 03/13/2012 |
| 8131762 | Method and system for metadata-driven document management and access control A system is provided to facilitate tag-based organization of documents. During operation, the system receives an original user query. The system extends the query to include documents with an IN-tag and exclude documents with an OUT-tag. The system then performs a s... | 03/06/2012 |
| 8131979 | Check-hazard instructions for processing vectors The described embodiments provide a system that determines data dependencies between two vector memory operations or two memory operations that use vectors of memory addresses. During operation, the system receives a first input vector and a second input vector. The... | 03/06/2012 |
| 8099582 | Tracking deallocated load instructions using a dependence matrix A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instru... | 01/17/2012 |
| 8082421 | Program instruction rearrangement methods in computer A program instruction rearrangement method calculates the dependency depth of each instruction of a program based on dependency between instructions, based on register access order, and rearranging instructions based on the dependency depth. Additionally, the depend... | 12/20/2011 |
| 8078843 | Facilitating processing in a computing environment using an extended drain instruction An extended DRAIN instruction is used to stall processing within a computing environment. The instruction includes an indication of the one or more processing stages at which processing is to be stalled. It also includes a control that allows processing to be stalle... | 12/13/2011 |
| 8078844 | System, method, and computer program product for removing a register of a processor from an active state A system, method, and computer program product are provided for removing a register of a processor from an active state. In operation, an aspect of a portion of a processor capable of simultaneously processing a plurality of threads is identified. Additionally, a re... | 12/13/2011 |
| 8046566 | Method to reduce power consumption of a register file with multi SMT support A method for reducing the power consumption of a register file of a microprocessor supporting simultaneous multithreading (SMT) is disclosed. Mapping logic and associated table entries monitor a total number of processing threads currently executing in the processor... | 10/25/2011 |
| 7971033 | Limiting entries in load issued premature part of load reorder queue searched to detect invalid retrieved values to between store safe and snoop safe pointers for the congruence class A method for reducing the number of load instructions in the load reorder queue (LRQ) that are searched when a load instruction is executed by a processor, including dispatching the load instructions; inserting the load instructions in the LRQ in program order; clea... | 06/28/2011 |
| 7966478 | Limiting entries in load reorder queue searched for snoop check to between snoop peril and tail pointers A method for reducing entries searched in a load reorder queue (LRQ) when snoop instructions are executed by a processor, including checking load reorder queue (LRQ) entries located between a load_peril_snoop register and a lrq_tail register for addresses matching t... | 06/21/2011 |
| 7958336 | System and method for reservation station load dependency matrix A device and method may fetch an instruction or micro-operation for execution. An indication may be made as to whether the instruction is dependent upon any source values corresponding to a set of previously fetched instructions. A value may be stored corresponding ... | 06/07/2011 |
| 7953960 | Method and apparatus for delaying a load miss flush until issuing the dependent instruction A pipeline processor has circuits to detect the presence of a register access instruction in an issue stage of the pipeline. A load-miss occurring at a later stage may cause the register access instruction to be marked with an associated bit. The register access ins... | 05/31/2011 |
| 7937565 | Method and system for data speculation on multicore systems The method and system for data speculation of multicore systems are disclosed. In one embodiment, a method includes dynamically determining whether a current speculative load instruction and an associated store instruction have same memory addresses in an applicatio... | 05/03/2011 |
| 7937564 | Emit vector optimization of a trace A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include associating a symbolic expression with each of at least a subset of the registers, holding a set of dependency indications that specify for ea... | 05/03/2011 |
| 7921278 | Early exit processing of iterative refinement algorithm using register dependency disable An “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algorithm, in ad... | 04/05/2011 |
| 7917736 | Latency tolerant pipeline synchronization A synchronization mechanism is used to synchronize events across multiple execution pipelines that process transaction streams. A common set of state configuration is included in each transaction stream to control processing of data that is distributed between the d... | 03/29/2011 |
| 7913066 | Early exit processing of iterative refinement algorithm using register dependency disable and programmable early exit condition A programmable “early exit” of an iterative refinement algorithm is implemented by effectively disabling read after write dependency stalls of newer instructions, as well as disabling the register write enable of these instructions, for the remainder of the algo... | 03/22/2011 |
| 7900023 | Technique to enable store forwarding during long latency instruction execution A technique to allow independent loads to be satisfied during high-latency instruction processing. Embodiments of the invention relate to a technique in which a storage structure is used to hold store operations in program order while independent load instructions a... | 03/01/2011 |
| 7882335 | System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipeline The present invention provides system and method for a group priority issue schema for a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group in ... | 02/01/2011 |
| 7877579 | System and method for prioritizing compare instructions The present invention provides a system and method for prioritizing compare instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue grou... | 01/25/2011 |
| 7870368 | System and method for prioritizing branch instructions The present invention provides a system and method for prioritizing branch instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group... | 01/11/2011 |
| 7865700 | System and method for prioritizing store instructions The present invention provides a system and method for prioritizing store instructions in a cascaded pipeline. The system includes a cascaded delayed execution pipeline unit having a plurality of execution pipelines that execute instructions in a common issue group ... | 01/04/2011 |
| 7849290 | Store queue architecture for a processor that supports speculative execution Embodiments of the present invention provide a system that buffers stores on a processor that supports speculative execution. The system starts by buffering a store into an entry in the store queue during a speculative execution mode. If an entry for the store does ... | 12/07/2010 |
| 7844799 | Method and system for pipeline reduction A method and system for operating a high frequency out-of-order processor with increased pipeline length. A new scheme is disclosed to reduce the pipeline by the detection and exploitation of so called “no dependency” for an instruction. A “no dependency” si... | 11/30/2010 |
| 7836279 | Method and system for supporting software pipelining using a shifting register queue A system for supporting software pipelining using a shifting register queue is provided. The system includes a register file that comprises a plurality of registers. The register file is operable to receive a shift mask signal and a shift signal and to identify a sh... | 11/16/2010 |
| 7836280 | Dynamic concurrent atomic execution Executing a set of one or more instructions atomically is disclosed. Executing includes determining whether speculatively executing the instructions is advised based at least in part on dynamic information associated with synchronization data and speculatively execu... | 11/16/2010 |
| 7831808 | Queue design system supporting dependency checking and issue for SIMD instructions within a general purpose processor A processor includes a general purpose (GP) unit adapted to receive and configured to execute GP instructions; and includes a single instruction multiple data (SIMD) unit adapted to receive and configured to execute SIMD instructions. An instruction unit comprises a... | 11/09/2010 |
| 7822950 | Thread cancellation and recirculation in a computer processor for avoiding pipeline stalls The present invention provides a computer pipeline control mechanism enabling a nonstalling pipeline despite the presence of pipeline hazards. The present invention detects the presence of predetermined pipeline hazard conditions, cancels the thread which contains t... | 10/26/2010 |
| 7809929 | Universal register rename mechanism for instructions with multiple targets in a microprocessor A universal register rename mechanism for instructions with multiple targets using a common destination tag. For each instruction that updates multiple destinations, a single rename entry is allocated to handle all destinations associated with it. A rename entry now... | 10/05/2010 |
| 7793081 | Implementing instruction set architectures with non-contiguous register file specifiers There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction ... | 09/07/2010 |
| 7779236 | Symbolic store-load bypass The invention provides a method and system for operating a pipelined microprocessor more quickly, by detecting instructions that load from identical memory locations as were recently stored to, without having to actually compute the referenced external memory addres... | 08/17/2010 |
| 7769985 | Load address dependency mechanism system and method in a high frequency, low power processor system The present invention provides for a method for a load address dependency mechanism in a high frequency, low power processor. A load instruction corresponding to a memory address is received. At least one unexecuted preceding instruction corresponding to the memory ... | 08/03/2010 |
| 7765384 | Universal register rename mechanism for targets of different instruction types in a microprocessor A unified register rename mechanism for targets of different instruction types is provided in a microprocessor. The universal rename mechanism renames destinations of different instruction types using a single rename structure. Thus, an instruction that is updating ... | 07/27/2010 |
