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| Number | Title | Issue Date |
| 8166279 | Method for predictive decoding of a load tagged pointer instruction Predictive decoding is achieved by fetching an instruction, accessing a predictor containing predictor information including prior instruction execution characteristics, obtaining predictor information for the fetched instruction from the predictor; and generating a... | 04/24/2012 |
| 8131977 | Microprocessor inhibiting instruction storage in cache and not decoding based on pre-analysis information to reduce power consumption A microprocessor includes: a processor core that performs pipeline processing; an instruction analyzing section that analyzes an instruction to be processed by the processor core and outputs analysis information indicating whether the instruction matches with a spec... | 03/06/2012 |
| 8122230 | Using a processor identification instruction to provide multi-level processor topology information Embodiments of an invention for using a processor identification instruction to provide multi-level processor topology information are disclosed. In one embodiment, a processor includes decode logic and control logic. The decode logic is to receive an identification... | 02/21/2012 |
| 8095777 | Structure for predictive decoding A design structure embodied in a machine readable medium used in a design process includes an apparatus for predictive decoding, the apparatus including register logic for fetching an instruction; predictor logic containing predictor information including prior inst... | 01/10/2012 |
| 8078841 | Parsing-enhancement facility using a translate-and-test instruction An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more gene... | 12/13/2011 |
| 8051274 | Processor and method of decompressing instruction bundle The description relates to an instruction fetch technology of a processor that processes a plurality of instructions in parallel. The processor exploits the use of a compression code fetched during a previous clock cycle when fetching compressed instructions from a ... | 11/01/2011 |
| 7987342 | Trace unit with a decoder, a basic-block cache, a multi-block cache, and sequencer An instruction processing circuit for a processor, where the instruction processing circuit is adapted to provide one or more sequence of operations, based on one or more sequence of instructions, to an execution circuit of the processor. The instruction processing ... | 07/26/2011 |
| 7949854 | Trace unit with a trace builder An instruction processing unit includes a trace builder circuit operable to (i) receive at least a portion of a first type of sequence of operations and to generate, based thereon, a second type of sequence of operations, where the portion includes at most one contr... | 05/24/2011 |
| 7945605 | Method for accelerating the computational speed of a computer algorithm A new technique for accelerating the computational speed of a computer algorithm is provided. The inventive technique can be applied to video compression/decompression algorithms, optical character recognition algorithms, and digital camera zooming applications.... | 05/17/2011 |
| 7937561 | Merge microinstruction for minimizing source dependencies in out-of-order execution microprocessor with variable data size macroarchitecture A microprocessor processes a macroinstruction that instructs the microprocessor to write an 8-bit result into only a lower 8 bits of an N-bit architected general purpose register. An instruction translator translates the macroinstruction into a merge microinstructio... | 05/03/2011 |
| 7913065 | Compression of processor instructions A custom processor is adapted for performing at least one predetermined application. The instruction sequence for the custom processor is compressed by performing at least one identification process on the instructions of the instruction sequence, in order to identi... | 03/22/2011 |
| 7865698 | Decode mode for an auxiliary processor unit controller in which an opcode is partially masked such that a configuration register defines a plurality of user defined instructions A method for decoding, including: obtaining an op-code from a master device; setting a mode to mask a first portion of the bits of the op-code, where the first portion of the bits are for being treated as a wildcard value; and decoding a second portion of the op-cod... | 01/04/2011 |
| 7844798 | Command protocol for integrated circuits A method of operating an integrated circuit involves supplying an instruction portion of a command to the integrated circuit to specify an operation to be performed by the integrated circuit. At least some types of commands also include an attributes portion that pr... | 11/30/2010 |
| 7814299 | Designating operands with fewer bits in instruction code by indexing into destination register history table for each thread A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target ... | 10/12/2010 |
| 7809928 | Generating event signals for performance register control using non-operative instructions One embodiment of an instruction decoder includes an instruction parser configured to process a first non-operative instruction and to generate a first event signal corresponding to the first non-operative instruction, and a first event multiplexer configured to rec... | 10/05/2010 |
| 7802078 | REP MOVE string instruction execution by selecting loop microinstruction sequence or unrolled sequence based on flag state indicative of low count repeat A microprocessor REP MOVS macroinstruction specifies the word length of the string in the IA-32 ECX register. The microprocessor includes a memory, configured to store a first and second sequence of microinstructions. The first sequence conditionally transfers contr... | 09/21/2010 |
| 7788471 | Data processor and methods thereof A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A selected arithmetic operation is performed on the operand vectors to produ... | 08/31/2010 |
| 7702885 | Firmware extendable commands including a test mode command for a microcontroller-based flash memory controller A system and method for expanding the command set of a memory controller is provided. In one implementation, the method includes decoding a first plurality of commands through a command decoding state machine, and in response to the command decoding state machine de... | 04/20/2010 |
| 7631166 | Processing instruction without operand by inferring related operation and operand address from previous instruction for extended precision computation A repeat instruction (RPT) operates on one or more operands, but the RPT instruction includes only an opcode and does not specify locations of the operand or operands. The type of operation to be performed when the RPT instruction is executed depends upon an initial... | 12/08/2009 |
| 7627741 | Instruction processing circuit including freezing circuits for freezing or passing instruction signals to sub-decoding circuits An instruction processing circuit includes an instruction decoder, with an instruction input coupled to an instruction source and a control output coupled to the control input of an execution circuit. The instruction decoder includes a predecoding circuit, multiple ... | 12/01/2009 |
| 7516304 | Parsing-enhancement facility An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more gene... | 04/07/2009 |
| 7493473 | Method of executing instructions using first and second control units that share a state register A method is provided for using a reconfigurable control structure that includes a hard-wired control unit configured to execute a pre-defined instruction set and a programmable control unit configured to execute a programmable instruction set. The method includes as... | 02/17/2009 |
| 7441099 | Configurable SIMD processor instruction specifying index to LUT storing information for different operation and memory location for each processing unit Methods and apparatuses for processing a Configurable Single-Instruction-Multiple-Data (CSIMD) instruction are disclosed. In the method, a lookup table (LUT) storing information is provided to support random access of memory locations associated with a plurality of ... | 10/21/2008 |
| 7441098 | Conditional execution of instructions in a computer A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of t... | 10/21/2008 |
| 7437532 | Memory mapped register file A memory mapped register file is disclosed for a data processing system that comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of registers addressable by an encoded address, wherein the encoded address corresponds to a res... | 10/14/2008 |
| 7434035 | Method and system for processing instructions in grouped and non-grouped modes An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instru... | 10/07/2008 |
| 7430678 | Low power operation control unit and program optimizing method An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit size or decoding time. An instruction code of each program for performin... | 09/30/2008 |
| 7401204 | Parallel Processor efficiently executing variable instruction word A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units pe... | 07/15/2008 |
| 7401176 | Method and system for fast access to stack memory Fast access of a memory having a stack uses an address bit, a stack pointer, and fast access random access memory (“RAM”). When a first address mode is used in conjunction with the address bit and the stack pointer, the location of the access RAM can be shifted ... | 07/15/2008 |
| 7398355 | Avoiding locks by transactionally executing critical sections One embodiment of the present invention provides a system that avoids locks by transactionally executing critical sections. During operation, the system receives a program which includes one or more critical sections which are protected by locks. Next, the system mo... | 07/08/2008 |
| 7395082 | Method and system for handling events in an application framework for a wireless device Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI wireless framework. An identity of the acquired MMI event may be deter... | 07/01/2008 |
| 7389405 | Digital signal processor architecture with optimized memory access for code discontinuity A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code discontinuity is encountered, the unified memory is accessed a first time ... | 06/17/2008 |
| 7383425 | Massively reduced instruction set processor This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video... | 06/03/2008 |
| 7376813 | Register move instruction for section select of source operand A data processing apparatus execution unit includes a multiplexer having inputs receiving data from sections of a source data register or registers. The multiplexer selects data from one section to store in a destination data register. The execution unit may zero ex... | 05/20/2008 |
| 7376818 | Program translator and processor Multiple instructions, specifying equivalent operations but designating different execution units, are stored beforehand on an instruction exchange table. First, a primary compiler compiles a source program into a set of machine-readable instructions. From the set o... | 05/20/2008 |
| 7373536 | Fine granularity halt instruction Systems and methods for halting the execution of instructions in a microprocessor are disclosed. The halt instruction may have an operand which allows a programmer to specify which clock of a system is to be utilized in conjunction with the halt instruction. A speci... | 05/13/2008 |
| 7369905 | Method and apparatus for pressure and plasma control during transitions used to create graded interfaces by multi-step PECVD deposition A method and apparatus are provided for a graded PECVD process that continuously modulates a set of flow and pressure conditions while the plasma power is turned on and a film is being deposited. A feedback mechanism specific to a give deposition recipe is used to g... | 05/06/2008 |
| 7366032 | Multi-ported register cell with randomly accessible history A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality... | 04/29/2008 |
| 7367057 | Processor based system and method for virus detection A processor based system and method for virus detection is described. In one embodiment, a processor comprises a plurality of functional units. The plurality of functional units includes a first functional unit and a second functional unit, the first functional unit... | 04/29/2008 |
| 7363476 | Method and apparatus to support an expanded register set According to an embodiment of the present invention, a microprocessor includes an expanded logical register set that can be accessed by instructions including legacy opcodes and remapped addressing mode information. The known IA-32 instruction set is limited to acce... | 04/22/2008 |
