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| Number | Title | Issue Date |
| 8185721 | Dual function adder for computing a hardware prefetch address and an arithmetic operation value A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The a... | 05/22/2012 |
| 8069336 | Transitioning from instruction cache to trace cache on label boundaries Various embodiments of methods and systems for implementing a microprocessor that includes a trace cache and attempts to transition fetching from instruction cache to trace cache only on label boundaries are disclosed. In one embodiment, a microprocessor may include... | 11/29/2011 |
| 7971031 | Data processing system and method A method, system and computer program for modifying an executing application, comprising monitoring the executing application to identify at least one of a hot load instruction, a hot store instruction and an active prefetch instruction that contributes to cache con... | 06/28/2011 |
| 7962724 | Branch loop performance enhancement A system and method for management of resource allocation for speculative fetched instructions following small backward branch instructions. An instruction fetch unit speculatively prefetches a memory line for each fetched memory line. Each memory line may have a sm... | 06/14/2011 |
| 7941638 | Facilitating fast scanning for control transfer instructions in an instruction fetch unit One embodiment of the present invention provides a system that performs a fast-scanning operation to generate fetch bundles within an instruction fetch unit (IFU) of a processor. During operation, the system obtains a cache line containing instructions at the IFU. N... | 05/10/2011 |
| 7941639 | Protection of the execution of a program A method for protecting the execution of a main program against possible traps, including, on occurrence of an instruction from the main program, starting a time counter of a given count according to next instructions of the main program, and executing, once the cou... | 05/10/2011 |
| 7925865 | Accuracy of correlation prefetching via block correlation and adaptive prefetch degree selection In the described embodiments, a method for prefetching data and/or instructions may include generating control flow information for each retired branch instruction. A correlation table may be maintained based on the generated control flow information and cache miss ... | 04/12/2011 |
| 7917731 | Method and apparatus for prefetching non-sequential instruction addresses A processor performs a prefetch operation on non-sequential instruction addresses. If a first instruction address misses in an instruction cache and accesses a higher-order memory as part of a fetch operation, and a branch instruction associated with the first instr... | 03/29/2011 |
| 7913064 | Operation frame filtering, building, and execution The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead... | 03/22/2011 |
| 7836277 | Pre-tracing instructions for CGA coupled processor in inactive mode for execution upon switch to active mode and continuing pre-fetching cache miss instructions A method of managing an instruction cache and a process of using the method are provided. The processor may comprise a processor core which is operated either during an active mode or during an inactive mode wherein the process core performs at least one instruction... | 11/16/2010 |
| 7831806 | Determining target addresses for instruction flow changing instructions in a data processing apparatus A data processing apparatus comprises a processor for executing a stream of instructions, and a prefetch unit for prefetching instructions from a memory prior to sending those instructions to the processor for execution. The prefetch unit receives from the memory a ... | 11/09/2010 |
| 7814298 | Promoting and appending traces in an instruction processing circuit based upon a bias value A method, system and computer program product for promoting a trace in an instruction processing circuit is disclosed. They comprise determining if a current trace is promotable and determining if a next trace is appendable to the current trace. They include promoti... | 10/12/2010 |
| 7805592 | Early resolving instructions Techniques are disclosed for handling control transfer instructions in pipelined processors. Such instructions may cause the sequence of subsequent instructions to change, and thus may require subsequent instructions to be deleted from the processor's pipeline. Pre-... | 09/28/2010 |
| 7802077 | Trace indexing via trace end addresses A new class traces for a processing engine, called “extended blocks,” possess an architecture that permits possible many entry points but only a single exit point. These extended blocks may be indexed based upon the address of the last instruction therein. Use o... | 09/21/2010 |
| 7779232 | Method and apparatus for dynamically managing instruction buffer depths for non-predicted branches A method and apparatus for dynamically managing instruction buffer depths for non-predicted branches reduces wasted energy and resources associated with low confidence branch prediction conditions. A portion of the instruction buffer for a instruction thread is allo... | 08/17/2010 |
| 7779234 | System and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor The present invention includes a system and method for implementing a hardware-supported thread assist under load lookahead mechanism for a microprocessor. According to an embodiment of the present invention, hardware thread-assist mode can be activated when one thr... | 08/17/2010 |
| 7779233 | System and method for implementing a software-supported thread assist mechanism for a microprocessor A system and computer-implementable method for implementing software-supported thread assist within a data processing system, wherein the data processing system supports processing instructions within at least a first thread and a second thread. An instruction dispa... | 08/17/2010 |
| 7707388 | Computer memory architecture for hybrid serial and parallel computing systems In one embodiment, a serial processor is configured to execute software instructions in a software program in serial. A serial memory is configured to store data for use by the serial processor in executing the software instructions in serial. A plurality of paralle... | 04/27/2010 |
| 7647477 | Branch target aware instruction prefetching technique Inspecting a currently fetched instruction group and determining branching behavior of the currently fetched instruction group, allows for intelligent instruction prefetching. A currently fetched instruction group is predecoded and, assuming the currently fetch inst... | 01/12/2010 |
| 7627740 | Methods and apparatus for dynamic prediction by software A method, storage medium, processor instruction and processor to for specifying a value in a first portion of a conditional pre-fetch instruction associated with a branch instruction used for effectuating a branch operation, specifying a target instruction address i... | 12/01/2009 |
| 7594096 | Load lookahead prefetch for microprocessors The present invention allows a microprocessor to identify and speculatively execute future load instructions during a stall condition. This allows forward progress to be made through the instruction stream during the stall condition which would otherwise cause the m... | 09/22/2009 |
| 7587580 | Power efficient instruction prefetch mechanism A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively ... | 09/08/2009 |
| 7555633 | Instruction cache prefetch based on trace cache eviction Various embodiments of methods and systems for implementing a microprocessor that fetches a group of instructions into instruction cache in response to a corresponding trace being evicted from the trace cache are disclosed. In some embodiments, a microprocessor may ... | 06/30/2009 |
| 7533247 | Operation frame filtering, building, and execution The present subject matter relates to operation frame filtering, building, and execution. Some embodiments include identifying a frame signature, counting a number of execution occurrences of the frame signature, and building a frame of operations to execute instead... | 05/12/2009 |
| 7529911 | Hardware-based technique for improving the effectiveness of prefetching during scout mode One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. Upon encountering a non-data dependent stall condition, the system performs a checkpoint and commences execution ... | 05/05/2009 |
| 7496732 | Method and apparatus for results speculation under run-ahead execution A method and apparatus for using result-speculative data under run-ahead speculative execution is disclosed. In one embodiment, the uncommitted target data from instructions being run-ahead executed may be saved into an advance data table. This advance data table ma... | 02/24/2009 |
| 7472256 | Software value prediction using pendency records of predicted prefetch values Profile information can be used to target read operations that cause a substantial portion of misses in a program. A software value prediction technique that utilizes latency and is applied to the targeted read operations facilitates aggressive speculative execution... | 12/30/2008 |
| 7461237 | Method and apparatus for suppressing duplicative prefetches for branch target cache lines A system that suppresses duplicative prefetches for branch target cache lines. During operation, the system fetches a first cache line into in a fetch buffer. The system then prefetches a second cache line, which immediately follows the first cache line, into the fe... | 12/02/2008 |
| 7441110 | Prefetching using future branch path information derived from branch prediction A mechanism is described that predicts the usefulness of a prefetching instruction during the instruction's decode cycle. Prefetching instructions that are predicted as useful (prefetch useful data) are sent to an execution unit of the processor for execution, while... | 10/21/2008 |
| 7437542 | Identifying and processing essential and non-essential code separately A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pi... | 10/14/2008 |
| 7434005 | Preload controller, preload control method for controlling preload of data by processor to temporary memory, and program A preload controller for controlling a bus access device that reads out data from a main memory via a bus and transfers the readout data to a temporary memory, including a first acquiring device to acquire access hint information which represents a data access inter... | 10/07/2008 |
| 7430650 | Generating a set of pre-fetch address candidates based on popular sets of address and data offset counters Cache prefetching algorithm uses previously requested address and data patterns to predict future data needs and prefetch such data from memory into cache. A requested address is compared to previously requested addresses and returned data to compute a set of increm... | 09/30/2008 |
| 7430640 | Detecting when to prefetch inodes and then prefetching inodes in parallel The decision to prefetch inodes is based upon the detecting of access patterns that would benefit from such a prefetch. Once the decision to prefetch is made, a plurality of inodes are prefetched in parallel. Further, the prefetching of inodes is paced, such that th... | 09/30/2008 |
| 7421540 | Method, apparatus, and program to efficiently calculate cache prefetching patterns for loops A mechanism is provided that identifies instructions that access storage and may be candidates for cache prefetching. The mechanism augments these instructions so that any given instance of the instruction operates in one of four modes, namely normal, unexecuted, da... | 09/02/2008 |
| 7418554 | Microprocessor with improved data stream prefetching A microprocessor coupled to a system memory by a bus includes an instruction decode unit that decodes an instruction that specifies a data stream in the system memory and a stream prefetch priority. The microprocessor also includes a load/store unit that generates l... | 08/26/2008 |
| 7409486 | Storage system, and storage control method A protocol chip and a bridge are connected to a first bus, while the bridge and a micro processor (MP) are connected to a second bus. The MP generates parameter information and writes it into a local memory (LM), and issues a write command which includes access dest... | 08/05/2008 |
| 7404042 | Handling cache miss in an instruction crossing a cache line boundary A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. Du... | 07/22/2008 |
| 7389405 | Digital signal processor architecture with optimized memory access for code discontinuity A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code discontinuity is encountered, the unified memory is accessed a first time ... | 06/17/2008 |
| 7383417 | Prefetching apparatus, prefetching method and prefetching program product The efficient performance of prefetching of data prior to the reading of the data by a program. A prefetching apparatus, for prefetching data from a file to a buffer before the data is read by a program, includes: a history recorder, for recording a history for a pl... | 06/03/2008 |
| 7373482 | Software-based technique for improving the effectiveness of prefetching during scout mode One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. During operation, the system executes program instructions in a normal-execution mode. Upon encountering a condit... | 05/13/2008 |
