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| Number | Title | Issue Date |
| 8171260 | Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction f... | 05/01/2012 |
| 7870367 | Methods and apparatus for implementing complex parallel instructions using control logic Methods and apparatus are provided for implementing complex parallel instructions on a processor having a supported instruction set. Complex parallel instructions provide that an operation code, control logic, and input data is passed to a processor core. The operat... | 01/11/2011 |
| 7836276 | System and method for processing thread groups in a SIMD architecture A SIMD processor efficiently utilizes its hardware resources to achieve higher data processing throughput. The effective width of a SIMD processor is extended by clocking the instruction processing side of the SIMD processor at a fraction of the rate of the data pro... | 11/16/2010 |
| 7673119 | VLIW optional fetch packet header extends instruction set space This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A predetermined one of these instructions is used as a special header. This special header has a unique encoding ... | 03/02/2010 |
| 7581082 | Software source transfer selects instruction word sizes This invention employs a 16-bit instruction set that has a subset of the functionality of the 32-bit instruction set. In this invention 16-bit instructions and 32-bit instructions can coexist in the same fetch packet. In the prior architecture 32-bit instructions ma... | 08/25/2009 |
| 7552314 | Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is decoded, which stores information about a control transfer instruction f... | 06/23/2009 |
| 7487333 | High-performance, superscalar-based computer system with out-of-order instruction execution A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program orde... | 02/03/2009 |
| 7454597 | Computer processing system employing an instruction schedule cache A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the instructions in the schedule, an order vector of an original order of the ... | 11/18/2008 |
| 7441103 | High-performance, superscalar-based computer system with out-of-order instruction execution A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program orde... | 10/21/2008 |
| 7424598 | Data processor The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machi... | 09/09/2008 |
| 7404042 | Handling cache miss in an instruction crossing a cache line boundary A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. Du... | 07/22/2008 |
| 7404048 | Inter-cluster communication module using the memory access network An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an ... | 07/22/2008 |
| 7401208 | Method and apparatus for randomizing instruction thread interleaving in a multi-thread processor A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency ... | 07/15/2008 |
| 7401207 | Apparatus and method for adjusting instruction thread priority in a multi-thread processor Each instruction thread in a SMT processor is associated with a software assigned base input processing priority. Unless some predefined event or circumstance occurs with an instruction being processed or to be processed, the base input processing priorities of the ... | 07/15/2008 |
| 7398374 | Multi-cluster processor for processing instructions of one or more instruction threads The invention provides a processor that processes bundles of instructions preferentially through clusters or execution units according to thread characteristics. The cluster architectures of the invention preferably include capability to process “multi-threaded”... | 07/08/2008 |
| 7383403 | Concurrent bypass to instruction buffers in a fine grain multithreaded processor In one embodiment, a processor comprises a plurality of instruction buffers, an instruction cache coupled to supply instructions to the plurality of instruction buffers, and a cache miss unit coupled to the instruction cache. Each of the plurality of instruction buf... | 06/03/2008 |
| 7373536 | Fine granularity halt instruction Systems and methods for halting the execution of instructions in a microprocessor are disclosed. The halt instruction may have an operand which allows a programmer to specify which clock of a system is to be utilized in conjunction with the halt instruction. A speci... | 05/13/2008 |
| 7366874 | Apparatus and method for dispatching very long instruction word having variable length Apparatus and method for dispatching a very long instruction word (VLIW) instruction having a variable length are provided. The apparatus for dispatching a VLIW instruction includes a packet buffer for storing at least one or more VLIW instructions, and a decoding u... | 04/29/2008 |
| 7366884 | Context switching system for a multi-thread execution pipeline loop and method of operation thereof A context switching system for a multi-thread execution pipeline loop having a pipeline latency and a method of operation thereof. In one embodiment, the context switching system includes a context switch requesting subsystem configured to: (1) detect a device reque... | 04/29/2008 |
| 7363481 | Information processing method for controlling the function of a plurality of processors, program for realizing the method, and recording medium There is provided an information processing method characterized in that, in accordance with an instruction from a host CPU 411, either a CPU 103 or 104 loads a common code and an instruction code defined to be executed by itself from an externa... | 04/22/2008 |
| 7363467 | Dependence-chain processing using trace descriptors having dependency descriptors An apparatus and method for a processor microarchitecture that quickly and efficiently takes large steps through program segments without fetching all intervening instructions. The microarchitecture processes descriptors of trace sequences in program order so as to ... | 04/22/2008 |
| 7363625 | Method for changing a thread priority in a simultaneous multithread processor An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority... | 04/22/2008 |
| 7360062 | Method and apparatus for selecting an instruction thread for processing in a multi-thread processor The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor events or conditions. During each processor clock cycle, an interleave r... | 04/15/2008 |
| 7360218 | System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. ... | 04/15/2008 |
| 7350027 | Architectural support for thread level speculative execution A method and apparatus for hardware support of the thread level speculation for existing processor cores without having to change the existing processor core, processor core's interface, or existing caches on the L1, L2 or L3 level. Architecture support for thread s... | 03/25/2008 |
| 7350056 | Method and apparatus for issuing instructions from an issue queue in an information handling system An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue inc... | 03/25/2008 |
| 7350030 | High performance chipset prefetcher for interleaved channels The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a cha... | 03/25/2008 |
| 7343595 | Method, apparatus and computer program for executing a program by incorporating threads There is provided a method for executing a program comprising a function call and one or more subsequent instructions. The method comprises processing, on a first thread, a function defined by the function call, the function having one or more programmer predefined ... | 03/11/2008 |
| 7337306 | Executing conditional branch instructions in a data processor having a clustered architecture There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control circuitry. Each of the clusters is capable of computing branch conditions, ... | 02/26/2008 |
| 7337304 | Processor for executing instruction control in accordance with dynamic pipeline scheduling and a method thereof When all of a plurality of instructions are symmetry instructions, a symmetry instruction issuing unit issues the symmetry instructions to a plurality of reservation stations provided for every different arithmetic operating units until they become full. If it is de... | 02/26/2008 |
| 7317656 | Semi-conductor memory component, and a process for operating a semi-conductor memory component The invention relates to a semi-conductor memory component and process for operating a semi-conductor memory component, including activating the memory cells of a memory cell array, when one or several memory cell(s) included in the first set of memory cells need(s)... | 01/08/2008 |
| 7281123 | Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second... | 10/09/2007 |
| 7268787 | Dynamic allocation of texture cache memory A graphics processing system has a cache which is partitionable into two or more slots. Once partitioned, the slots are dynamically allocatable to one or more texture maps. First, number of texture maps needed to render a given scene is determined. Then, available s... | 09/11/2007 |
| 7257807 | Method for optimizing execution time of parallel processor programs The present invention is directed to a parallel processor language, a method for translating C++ programs into a parallel processor language, and a method for optimizing execution time of a parallel processor program. In an exemplary aspect of the present invention,... | 08/14/2007 |
| 7254689 | Decompression of block-sorted data In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a plurality of paths through a mapping array T are being handled by a pr... | 08/07/2007 |
| 7254690 | Pipelined semiconductor memories and systems The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or... | 08/07/2007 |
| 7237095 | Optimum power efficient shifting algorithm for schedulers A method and mechanism for managing shifts in a shifting queue. A reservation station in a processing device includes a queue of shifting entries. On a given cycle, zero, one, or two instructions may be dispatched and stored in the queue. Depending upon the dispatch... | 06/26/2007 |
| 7234042 | Identification bit at a predetermined instruction location that indicates whether the instruction is one or two independent operations and indicates the nature the operations executing in two processing channels An instruction set for a computer is described which includes instructions having a common predetermined bit length. That predetermined bit length can define a single operation or two independent operations. The instruction includes designated bits at predetermined ... | 06/19/2007 |
| 7234025 | Microprocessor with repeat prefetch instruction A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction. The instruction is specified by the Pentium III PREFETCH opcode preced... | 06/19/2007 |
| 7219185 | Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cache A processor having the capability to dispatch multiple parallel operations, including multiple load operations, accesses a cache which is divided into banks. Each bank supports a limited number of simultaneous read and write access operations. A bank prediction fiel... | 05/15/2007 |
