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| Number | Title | Issue Date |
| 8176297 | Adaptive fetch advance control for a low power processor A digital signal processor (DSP) includes an instruction buffer queue (IBQ) with multiple lines, as well as a modifiable fetch advance parameter to specify a fetch advance setting for the IBQ. The DSP also has a control flow module. In response to execution of a pro... | 05/08/2012 |
| 8131976 | Tracking effective addresses in an out-of-order processor Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an instruction from an instruction cache and associating, by an effective ad... | 03/06/2012 |
| 8078840 | Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a given selection cycle, some of the threads may not be requesting to fetc... | 12/13/2011 |
| 8069335 | Processing system and method for executing instructions A processing system for executing instructions comprises a first part (11) having address information and a plurality of data bits, E0 to EN. According to one embodiment, each data bit E0 to EN directly selects a co... | 11/29/2011 |
| 8006070 | Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the accuracy of branch predictions of branch instructions therein that is less ... | 08/23/2011 |
| 7979675 | Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update ... | 07/12/2011 |
| 7962722 | Branch target address cache with hashed indices In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches instructions from a memory system for execution by the at least one exe... | 06/14/2011 |
| 7962723 | Methods and apparatus storing expanded width instructions in a VLIW memory deferred execution Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved ind... | 06/14/2011 |
| 7958334 | Method and apparatus for an efficient multi-path trace cache design A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency... | 06/07/2011 |
| 7958333 | Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected A processor and method for executing threads. The processor comprises multiple instruction buffers, each for buffering the instructions of a respective associated thread, and an instruction issue stage for issuing instructions from the instruction buffers to a memor... | 06/07/2011 |
| 7877577 | Information processor and instruction fetch control method In implementing an encryption algorithm or the like in a computer, it is difficult to align timing at which an instruction is executed regardless of presence or absence of branch in a case of including a conditional branch instruction. In order to solve the problem,... | 01/25/2011 |
| 7873813 | Variable length VLIW instruction with instruction fetch control bits for prefetching, stalling, or realigning in order to handle padding bits and instructions that cross memory line boundaries A computer system with a processing unit and a memory. The processing unit is arranged to fetch memory lines from the memory and execute instructions from the memory lines. Each memory line is fetched as a whole and is capable of holding more than one instruction. A... | 01/18/2011 |
| 7822949 | Command supply device that supplies a command read out from a main memory to a central processing unit A command supply device supplies a command sequence that forms a loop. A loop command buffer accumulates a first partial command sequence. The first partial command sequence is a head part of a first command sequence repeatedly supplied to a CPU from among command s... | 10/26/2010 |
| 7802076 | Method and apparatus to vectorize multiple input instructions An optimization unit to search for two or more candidate instructions in an instruction trace and to merge the two or more candidate instructions into a single instruction with multiple data (SIMD) according to a depth of a trace dependency and a common operation co... | 09/21/2010 |
| 7779231 | Pipelined processing using option bits encoded in an instruction A processor and a method for executing VLIW instructions using pipeline execution wherein each VLIW instruction includes a plurality of instructions and wherein the pipeline includes at least the following stages: first and second instruction fetch stages, a pre-dec... | 08/17/2010 |
| 7752422 | Execution of instructions directly from input source A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12)... | 07/06/2010 |
| 7676650 | Apparatus for controlling instruction fetch reusing fetched instruction When an instruction stored in a specific instruction buffer is the same as another instruction stored in another instruction buffer and logically subsequent to the instruction in the specific instruction buffer, a connection is made from the instruction buffer stori... | 03/09/2010 |
| 7640418 | Dynamic field patchable microarchitecture A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for the selection of corresponding ROM or RAM microcode for execution. A mu... | 12/29/2009 |
| 7577824 | Methods and apparatus for storing expanded width instructions in a VLIW memory for deferred execution Techniques are described for decoupling fetching of an instruction stored in a main program memory from earliest execution of the instruction. An indirect execution method and program instructions to support such execution are addressed. In addition, an improved ind... | 08/18/2009 |
| 7552313 | VLIW digital signal processor for achieving improved binary translation A VLIW digital signal processor is composed of a program memory including first to n-th banks, first to n-th address counters, a fetch block, and an instruction executing section. The first to n-th banks store therein first to n-th programs, respectively. The first ... | 06/23/2009 |
| 7484077 | Skipping unnecessary instruction by multiplex selector using next instruction offset stride signal generated from instructions comparison results The present invention discloses an apparatus for removing unnecessary instruction and method thereof. The apparatus and operating method thereof include: a comparing circuit for comparing a plurality of instructions and a predetermined pattern, so as to generate a p... | 01/27/2009 |
| 7454596 | Method and apparatus for partitioned pipelined fetching of multiple execution threads Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a thread from a plurality of execution threads. In one embodiment, storag... | 11/18/2008 |
| 7447876 | System and method for handling load and/or store operations in a superscalar microprocessor The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose i... | 11/04/2008 |
| 7441101 | Thread-aware instruction fetching in a multithreaded embedded processor The present invention provides a multithreaded processor, such as a network processor, that fetches instructions in a pipeline stage based on feedback signals from later stages. The multithreaded processor comprises a pipeline with an instruction unit in the early s... | 10/21/2008 |
| 7441102 | Integrated circuit with functional state configurable memory and method of configuring functional states of the integrated circuit memory An integrated circuit comprises a processor configured for fetching and executing opcodes, a system bus, and a memory coupled to the processor via the system bus. The memory includes logic circuitry for detecting functional states of the memory, wherein the memory (... | 10/21/2008 |
| 7434035 | Method and system for processing instructions in grouped and non-grouped modes An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instru... | 10/07/2008 |
| 7434029 | Inter-processor control A system includes a first processor coupled to a second processor. The first and second processors are coupled to memory. The first processor fetches and executes supported instructions until an unsupported instruction is detected. The second processor executes the ... | 10/07/2008 |
| 7406585 | Data processing system having an external instruction set and an internal instruction set There is provided a system having an execution core operable to execute internal instructions. A translation buffer is operable to store a plurality of internal instruction blocks of one or more internal instructions where the internal instruction bloc... | 07/29/2008 |
| 7404042 | Handling cache miss in an instruction crossing a cache line boundary A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. Du... | 07/22/2008 |
| 7376819 | Data processor with selectable word length An apparatus and method for selecting whether a central processing unit (CPU) performs instruction reading in units of 16 bits (a first word length) or in units of 32 bits (a second word length). Depending on whether instruction reading is performed in units of 16 b... | 05/20/2008 |
| 7373489 | Apparatus and method for floating-point exception prediction and recovery An apparatus and method for floating point exception prediction and recovery. In one embodiment, a processor may include instruction fetch logic configured to issue a first instruction from one of a plurality of threads and to successively issue a second instruction... | 05/13/2008 |
| 7366875 | Method and apparatus for an efficient multi-path trace cache design A novel trace cache design and organization to efficiently store and retrieve multi-path traces. A goal is to design a trace cache, which is capable of storing multi-path traces without significant duplication in the traces. Furthermore, the effective access latency... | 04/29/2008 |
| 7366878 | Scheduling instructions from multi-thread instruction buffer based on phase boundary qualifying rule for phases of math and data access operations with better caching A processor buffers asynchronous threads. Current instructions requiring operations provided by a plurality of execution units are divided into phases, each phase having at least one math operation and at least one texture cache access operation. Instructions within... | 04/29/2008 |
| 7366880 | Facilitating value prediction to support speculative program execution One embodiment of the present invention provides a system that predicts a result produced by a section of code in order to support speculative program execution. The system begins by executing the section of code using a head thread in order to produce a result. Bef... | 04/29/2008 |
| 7363369 | Monitoring thread usage to dynamically control a thread pool A method, system, and program for monitoring thread usage to dynamically control a thread pool are provided. An application running on the server system invokes a listener thread on a listener socket for receiving client requests at the server system and passing the... | 04/22/2008 |
| 7363625 | Method for changing a thread priority in a simultaneous multithread processor An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority... | 04/22/2008 |
| 7360059 | Variable width alignment engine for aligning instructions based on transition between buffers In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. ... | 04/15/2008 |
| 7356674 | Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine A method of, and apparatus for, interfacing the hardware of a processor capable of processing instructions from more than one type of instruction set. More particularly, an engine responsible for fetching native instructions from a memory subsystem (such as an EM fe... | 04/08/2008 |
| 7353339 | Adaptive caching Provided are techniques for cache management. An incoming request to access a first data block is received. A probability of how likely a second data block may be accessed based on the access of the first data block is determined. Whether the probability exceeds a r... | 04/01/2008 |
| 7353364 | Apparatus and method for sharing a functional unit execution resource among a plurality of functional units An apparatus and method for sharing a functional unit. In one embodiment, a processor may include instruction fetch logic configured to issue instructions, and a first functional unit configured to execute instructions issued from the instruction fetch logic and to ... | 04/01/2008 |
