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| Number | Title | Issue Date |
| 8095776 | Semiconductor device and data processing system selectively operating as one of a big endian or little endian system A semiconductor device correctly switches endian modes regardless of the current endian mode of an interface. The semiconductor device includes a switching circuit and a first register. The switching circuit switches an interface to be used in big endian or little e... | 01/10/2012 |
| 7934077 | Semiconductor device and data processing system selectively operating as one of a big endian or little endian system The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The s... | 04/26/2011 |
| 7793077 | Alignment and ordering of vector elements for single instruction multiple data processing The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit int... | 09/07/2010 |
| 7757066 | System and method for executing variable latency load operations in a date processor There is disclosed a data processor that executes variable latency load operations using bypass circuitry that allows load word operations to avoid stalls caused by shifting circuitry. The processor comprises: 1) an instruction execution pipeline comprising N proces... | 07/13/2010 |
| 7685407 | Semiconductor device and data processing system selectively operating as one of a big endian or little endian system The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The s... | 03/23/2010 |
| 7640417 | Instruction length decoder Methods and apparatus relating to speculatively decoding instruction lengths in order to increase instruction throughput are described. In an embodiment, instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instr... | 12/29/2009 |
| 7624251 | Instructions for efficiently accessing unaligned partial vectors One embodiment of the present invention provides a processor that is configured to execute load-swapped-partial instructions. An instruction fetch unit within the processor is configured to fetch the load-swapped-partial instruction to be executed. Note that the loa... | 11/24/2009 |
| 7620797 | Instructions for efficiently accessing unaligned vectors One embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is configured to execute the load-swapped instruction by loading a vector fr... | 11/17/2009 |
| 7565510 | Microprocessor with a register selectively storing unaligned load instructions and control method thereof A load/store unit includes a Top register for storing a value retained before loading to a load destination register and a saved register capable of storing data retained to the Top register. When an unaligned instruction evaluation unit determines that a load instr... | 07/21/2009 |
| 7473293 | Processor for executing instructions containing either single operation or packed plurality of operations dependent upon instruction status indicator A conversion table converts a packed instruction (pre-conversion code) contained in the instruction code fetched from an instruction memory into a plurality of instruction codes (converted codes). An instruction decoder decodes the plurality of the instruction codes... | 01/06/2009 |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7437537 | Methods and apparatus for predicting unaligned memory access In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The add... | 10/14/2008 |
| 7412584 | Data alignment micro-architecture systems and methods Systems and methods are disclosed for aligning data in memory access and other applications. In one embodiment a system is provided that includes a memory unit, a shifter, and control logic operable to route data from the memory unit to the shifter and to send an in... | 08/12/2008 |
| 7404042 | Handling cache miss in an instruction crossing a cache line boundary A fetch section of a processor comprises an instruction cache and a pipeline of several stages for obtaining instructions. Instructions may cross cache line boundaries. The pipeline stages process two addresses to recover a complete boundary crossing instruction. Du... | 07/22/2008 |
| 7404019 | Method and apparatus for endianness control in a data processing system A method for providing endianness control in a data processing system includes initiating an access which accesses a peripheral, providing a first endianness control that corresponds to the peripheral, and completing the access using the endianness control to affect... | 07/22/2008 |
| 7392366 | Adaptive fetch gating in multithreaded processors, fetch control and method of controlling fetches A multithreaded processor, fetch control for a multithreaded processor and a method of fetching in the multithreaded processor. Processor event and use (EU) signs are monitored for downstream pipeline conditions indicating pipeline execution thread states. Instructi... | 06/24/2008 |
| 7392337 | System, method and storage medium for a memory subsystem command interface A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of ... | 06/24/2008 |
| 7386706 | System and software for matched aligned and unaligned storage instructions A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements in partitione... | 06/10/2008 |
| 7360059 | Variable width alignment engine for aligning instructions based on transition between buffers In one embodiment, a digital signal processor includes look ahead logic to decrease the number of bubbles inserted in the processing pipeline. The processor receives data containing instructions in a plurality of buffers and decodes the size of a first instruction. ... | 04/15/2008 |
| 7353371 | Circuit to extract nonadjacent bits from data packets A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination data fields in a result packet governed by a field locator packet. I... | 04/01/2008 |
| 7350056 | Method and apparatus for issuing instructions from an issue queue in an information handling system An information handling system includes a processor that issues instructions out of program order. The processor includes an issue queue that may advance instructions toward issue even though some instructions in the queue are not ready-to-issue. The issue queue inc... | 03/25/2008 |
| 7343473 | System and method for translating non-native instructions to native instructions for processing on a host processor A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The s... | 03/11/2008 |
| 7340589 | Shift prefix instruction decoder for modifying register information necessary for decoding the target instruction The data processing device and electronic equipment of the present invention perform pipeline control and include a fetch circuit which fetches instruction codes of a plurality of instructions in instruction queues. A prefix instruction decoder circuit performs a de... | 03/04/2008 |
| 7337272 | Method and apparatus for caching variable length instructions An instruction cache controller uses supplemental memory to store a redundant copy of cached instruction data corresponding to a cache boundary position, and thereby enables subsequent single cache access retrieval of an instruction that crosses that boundary positi... | 02/26/2008 |
| 7334066 | Computer system providing endian information and method of data transmission thereof A computer system providing endian information and a method of data transmission thereof are disclosed. The method of data transmission in the computer system of the present invention comprises: reading endian information stored in a base address register of periphe... | 02/19/2008 |
| 7330959 | Use of MTRR and page attribute table to support multiple byte order formats in a computer system Computer technology supports multiple byte order formats, separately or simultaneously. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. The PAT has a plurality of entries. Each entry indicates a memo... | 02/12/2008 |
| 7328433 | Methods and apparatus for reducing memory latency in a software application Methods and apparatus for reducing memory latency in a software application are disclosed. A disclosed system uses one or more helper threads to prefetch variables for a main thread to reduce performance bottlenecks due to memory latency and/or a cache miss. A perfo... | 02/05/2008 |
| 7305542 | Instruction length decoder Speculatively decoding instruction lengths in order to increase instruction throughput. Instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor cl... | 12/04/2007 |
| 7302552 | System for processing VLIW words containing variable length instructions having embedded instruction length identifiers A processor is described including a plurality of data path elements which independently perform in parallel different data processing operations. Program instructions are provided which are decoded to generate control signals for controlling the data path elements.... | 11/27/2007 |
| 7296108 | Apparatus and method for efficient transmission of unaligned data An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment mechanism is provided in the bus interface of the receiving processo... | 11/13/2007 |
| 7293177 | Preventing virus infection in a computer system A method of preventing an electronic file containing a computer virus from infecting a computer system using the Symbian™ operating system, the method comprising the steps of scanning files using an anti-virus application, and if an infected file is identified, ma... | 11/06/2007 |
| 7284116 | Method and system for safe data dependency collapsing based on control-flow speculation The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved based on actual data values, the conditional branch prediction provi... | 10/16/2007 |
| 7278140 | Apparatus and method of updating data of an embedded system, and apparatus for updating data of memory An apparatus and a method for updating data in an embedded system are provided. The apparatus includes a processor for retrieving new data and a transmission line. The transmission line connects to the processor to receive the new data and transmits the new data to ... | 10/02/2007 |
| 7278014 | System and method for simulating hardware interrupts A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, call... | 10/02/2007 |
| 7275147 | Method and apparatus for data alignment and parsing in SIMD computer architecture Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a shift value, preferably as parameters of the instruction. A first and... | 09/25/2007 |
| 7272675 | First-in-first-out (FIFO) memory for buffering packet fragments through use of read and write pointers incremented by a unit access and a fraction of the unit access Disclosed is an apparatus and method used in an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments, comprising a first-in-first-out (FIFO) memory, a read pointer of the FIFO memory, the read pointer to increment by at least ... | 09/18/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7254704 | Tracing through reset A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be ... | 08/07/2007 |
| 7249352 | Apparatus and method for removing elements from a linked list Methods, apparatus and computer program products for removal of elements from a linked list while other elements of the linked list are allowed to be accessed during the removal operation. In one embodiment, the method, apparatus and computer program product include... | 07/24/2007 |
| 7249252 | Method of replacing initialization code in a control store with main code after execution of the initialization code has completed A method includes loading initialization code into a control store in an embedded microprocessor and executing the initialization code. The method determines if the execution of the initialization code is complete and replaces the initialization code in the control ... | 07/24/2007 |
