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| Number | Title | Issue Date |
| 7822948 | Apparatus, system, and method for discontiguous multiple issue of instructions An apparatus, system, and method are disclosed for discontiguous multiple issue of instructions. An assignment unit assigns a plurality of instruction blocks to a plurality of issue units. The plurality of issue units each comprises a renaming map that maps each arc... | 10/26/2010 |
| 7484076 | Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q Methods, apparatuses, and systems are presented for performing instructions using multiple execution units in a graphics processing unit involving issuing an instruction for P executions of the instruction wherein each execution uses different data, P being a positi... | 01/27/2009 |
| 7436559 | Load assignment in image processing by parallel processing In image processing carried out by means of repeated execution of process set which includes N unit processes (where N is an integer equal to 3 or greater), prior to execution of the process groups, the N unit processes are assigned to a number M (where M is an inte... | 10/14/2008 |
| 7404048 | Inter-cluster communication module using the memory access network An inter-cluster communication module using the memory access network is provided, including a plurality of clusters, a memory subsystem, a controller and a switch device. When some clusters issue a load instruction and some clusters issue a store instruction of an ... | 07/22/2008 |
| 7395408 | Parallel execution processor and instruction assigning making use of group number in processing elements The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one instruction to all the PEs. When the piece of instruction data... | 07/01/2008 |
| 7395412 | Apparatus and method for extending data modes in a microprocessor An apparatus and method are provided for extending a microprocessor instruction set beyond its current capabilities to allow for extended size operands specifiable by programmable instructions in the microprocessor instruction set. The apparatus includes translation... | 07/01/2008 |
| 7373640 | Technique for dynamically restricting thread concurrency without rewriting thread code The present invention provides a technique for converting a multi-threaded application configured to execute on a uniprocessor (UP) system to one that executes on a multiprocessor (MP) system. Unlike previous approaches, a novel scheduling technique is employed so t... | 05/13/2008 |
| 7363546 | Latent fault detector A latent error detector may be configured to reveal latent errors within a plurality of components within a computer system. The latent error detector may be configured to access configuration data specifying one or more types of components and one or more modules f... | 04/22/2008 |
| 7363260 | Method and apparatus providing automatic provisioning for modular network devices A method of provisioning modular network devices is described. A generic configuration is placed on a device; the configuration comprises commands for configuring interfaces associated the device. At the device, each interface associated with the device is configure... | 04/22/2008 |
| 7340588 | Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page int... | 03/04/2008 |
| 7331045 | Scheduling technique for software pipelining An improved scheduling technique for software pipelining is disclosed which is designed to find schedules requiring fewer processor clock cycles and reduce register pressure hot spots when scheduling multiple groups of instructions (e.g. as represented by multiple s... | 02/12/2008 |
| 7325228 | Data speculation across a procedure call using an advanced load address table A method of converting an original code sequence to a modified code sequence where the original code sequence includes a procedure call that is prior to a load instruction to one of a first plurality of registers is provided. The method includes inserting the load i... | 01/29/2008 |
| 7302548 | System and method for communicating in a multi-processor environment A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the o... | 11/27/2007 |
| 7302551 | Suppression of store checking An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruc... | 11/27/2007 |
| 7302557 | Method and apparatus for modulo scheduled loop execution in a processor architecture A processor method and apparatus that allows for the overlapped execution of multiple iterations of a loop while allowing the compiler to include only a single copy of the loop body in the code while automatically managing which iterations are active. Since the prol... | 11/27/2007 |
| 7278009 | Tiered sequential processing media data through multiple processor chains with longest path tier assignment of processors Tiered command distribution is described. In an embodiment, a pipeline architecture includes processor chains of data processors that process control events received from an application interface control. A tier assignment algorithm determines the longest path of da... | 10/02/2007 |
| 7275246 | Executing programs for a first computer architecture on a computer of a second architecture Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context... | 09/25/2007 |
| 7266487 | Matched instruction set processor systems and method, system, and apparatus to efficiently compile hardware and software designs This invention relates to matched instruction set processor systems and method, system, and apparatus to efficiently compile hardware and software designs. A method to efficiently design and implement a matched instruction set processor system includes analyzing and... | 09/04/2007 |
| 7254806 | Detecting reordered side-effects A computer binary translator translates at least a segment of a binary representation of a program from a first instruction set architecture to a second instruction set architecture. A sequence of side-effects in the translation differs from a sequence of side-effec... | 08/07/2007 |
| 7249352 | Apparatus and method for removing elements from a linked list Methods, apparatus and computer program products for removal of elements from a linked list while other elements of the linked list are allowed to be accessed during the removal operation. In one embodiment, the method, apparatus and computer program product include... | 07/24/2007 |
| 7243333 | Method and apparatus for creating and executing integrated executables in a heterogeneous architecture The present invention provides a compilation system for compiling and linking an integrated executable adapted to execute on a heterogeneous parallel processor architecture. The compiler and linker compile different segments of the source code for a first and second... | 07/10/2007 |
| 7234042 | Identification bit at a predetermined instruction location that indicates whether the instruction is one or two independent operations and indicates the nature the operations executing in two processing channels An instruction set for a computer is described which includes instructions having a common predetermined bit length. That predetermined bit length can define a single operation or two independent operations. The instruction includes designated bits at predetermined ... | 06/19/2007 |
| 7234018 | Layered crossbar for interconnection of multiple processors and shared memories A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each ha... | 06/19/2007 |
| 7231509 | Extended register bank allocation based on status mask bits set by allocation instruction for respective code block An extended register processor includes a register file having a legacy register set and an extended register set. The extended register set includes a plurality of extended registers accessible only to extended register instructions. The processor maps extended reg... | 06/12/2007 |
| 7228404 | Managing instruction side-effects A computer. When an instruction calling for an architecturally-visible side-effect in an architecturally-visible storage location is recognized, a value is stored representative of an architecturally-visible representation of the side-effect, a format of the represe... | 06/05/2007 |
| 7225431 | Method and apparatus for setting breakpoints when debugging integrated executables in a heterogeneous architecture The present invention provides inserting and deleting a breakpoint in a parallel processing system. A breakpoint is inserted in a module loaded into the execution environment of an attached processor unit. The breakpoint can be inserted directly. Furthermore, the un... | 05/29/2007 |
| 7222332 | Method and apparatus for overlay management within an integrated executable for a heterogeneous architecture The present invention provides for creating and employing code and data partitions in a heterogeneous environment. This is achieved by separating source code and data into at least two partitioned sections and at least one unpartitioned section. Generally, a partiti... | 05/22/2007 |
| 7206950 | Processor system, instruction sequence optimization device, and instruction sequence optimization program To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section detects an assignment control flag and a clock control flag added to instruction code. An instruction assign... | 04/17/2007 |
| 7191310 | Parallel processor and image processing apparatus adapted for nonlinear processing through selection via processor element numbers A parallel processor includes a global processor which interprets a program and controls the entirety of the parallel processor. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processin... | 03/13/2007 |
| 7185174 | Switch complex selectively coupling input and output of a node in two-dimensional array to four ports and using four switches coupling among ports A switching element for switchably coupling a two-dimensional array of circuit elements comprises an input, an output, means for switchably coupling the input to the output; a first input/output port, a second input/output port, a third input/output port, and a four... | 02/27/2007 |
| 7178009 | Different register data indicators for each of a plurality of central processing units A digital signal processor may include a plurality of processing elements that are coupled together to accomplish a specialized function. Each processing element may utilize the same shared storage in a form of a plurality of general purpose registers. Each of these... | 02/13/2007 |
| 7152124 | Method and system for maintaining temporal consistency of resources and data in a multiple-processor packet switch A network switch architected using multiple processor engines includes a method and system for ensuring temporal consistency of data and resources as packet traffic flows through the switch. Upon receiving a connection request, the switch internally associates a sem... | 12/19/2006 |
| 7139832 | Data transfer and intermission between parent and child process A data transfer method realizing a function similar to Unix's FORK by the following operations: allowing a parent process on a server to issue a request for intermission of communication to a process on a client and allowing the process on the client to issue a repo... | 11/21/2006 |
| 7137110 | Profiling ranges of execution of a computer program Profiling execution of a program. The program is coded in a mode-dependent instruction set. During a profile-quiescent execution interval, the profile circuitry records no profile information. After a triggering event is detected, the profile circuitry commences a p... | 11/14/2006 |
| 7137111 | Aggressive prefetch of address chains Operations including inserted prefetch operations that correspond to addressing chains may be scheduled above memory access operations that are likely-to-miss, thereby exploiting latency of the “martyred” likely-to-miss operations and improving execution perform... | 11/14/2006 |
| 7137109 | System and method for managing access to a controlled space in a simulator environment In one embodiment, the invention may comprise a computer-implemented system for managing access to a controlled space in a simulator environment, comprising: means for requiring initialization of a simulated hardware control object by a user code application operabl... | 11/14/2006 |
| 7127588 | Apparatus and method for an improved performance VLIW processor In one exemplary embodiment, the disclosed VLIW processor comprises a number of threads where each thread includes a processing unit. For example, there can be two threads, where each of the two threads has its own processing unit. According to this exemplary embodi... | 10/24/2006 |
| 7127594 | Multiprocessor system and program optimizing method A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information indicating the program control mode, a VLIW mode or a multithread mode, in a p... | 10/24/2006 |
| 7124279 | Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions Instructions of a program are stored in compressed form in a program memory. A cache loading unit includes a decompression section and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memo... | 10/17/2006 |
| 7114062 | Processor which accelerates execution of binary programs intended for execution on a conventional processor core, using a reconfigurable combinational logic array, a function lookup unit, and a compatible conventional processor core, without requiring recompilation The invention uses a standard processor to execute an application program. As the instructions of the application program are executed in sequence, a program counter is incremented to contain an address indicator of the next instruction to be executed. The address i... | 09/26/2006 |
