Did You Know...
...that while attempting to develop a super strong glue, 3M employee Spencer Silver accidentally developed a glue that was so weak it would barely hold two pieces of paper together? However, his colleague Art Fry needed the glue. Fry sang with his church choir and marked the pages of his hymnal with small scraps of paper that often fell out. He used Silver's glue to hold the papers in place. Today we call this invention Post-it Notes.
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| Number | Title | Issue Date |
| 7975127 | Computer system for processing instructions each containing a group of operations to be executed out of order A computer system comprising a data file having entries each of which is designed to hold data, an advanced and a completed mapping file each having entries each of which is designed to hold a data-file-entry address, an operation window that is a buffer to hold sub... | 07/05/2011 |
| 7840782 | Mixed stack-based RISC processor A processor (e.g., a co-processor) executes a stack-based instruction set and another instruction in a way that accelerates the execution of the stack-based instruction set, although code acceleration is not required under the scope of this disclosure. In accordance... | 11/23/2010 |
| 7685406 | Determination of current stack pointer value using architectural and speculative stack pointer delta values A technique for reducing stack pointer adjustment operations when stack dependent operations, which correspond to stack dependent instructions, are encountered includes setting a stack pointer to an initial value for a stack. A number of bytes associated with the st... | 03/23/2010 |
| 7617383 | Circular register arrays of a computer A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom reg... | 11/10/2009 |
| 7539849 | Maintaining a double-ended queue in a contiguous array with concurrent non-blocking insert and remove operations using a double compare-and-swap primitive An array-based concurrent shared object implementation has been developed that provides non-blocking and linearizable access to the concurrent shared object. In an application of the underlying techniques to a deque, the array-based algorithm allows uninterrupted co... | 05/26/2009 |
| 7447875 | Method and system for management of global queues utilizing a locked state A method and system for managing global queues is provided. In one example, a method for implementing a global queue is provided. The queue has a head pointer, a tail pointer, and zero or more elements. The method comprises one or more functions for managing the que... | 11/04/2008 |
| 7424600 | Information processing apparatus, information processing method, and program conversion apparatus, in which stack memory is used with improved efficiency The information processing apparatus includes: a process unit having one or more registers that retain data used for calculation; a compression unit that compresses and saves the content in the register to a stack memory; and a decompression unit that decompresses a... | 09/09/2008 |
| 7424596 | Code interpretation using stack state information Executing an instruction on an operand stack, including performing a stack-state aware translation of the instruction to threaded code to determine an operand stack state for the instruction, dispatching the instruction according to the operand stack state for the i... | 09/09/2008 |
| 7415602 | Apparatus and method for processing a sequence of jump instructions An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining t... | 08/19/2008 |
| 7406592 | Method, system, and apparatus for efficient evaluation of boolean expressions Methods, systems, and computer-readable media are provided for efficiently evaluation Boolean expressions. According to the method, the Boolean expression is expressed using pre-fix notation. Each element in the pre-fix expression is then parsed. For each first oper... | 07/29/2008 |
| 7380245 | Technique for detecting corruption associated with a stack in a storage device A technique for detecting corruption associated with a stack in a storage device is disclosed. In one embodiment, the technique is realized by having a processing device insert a quantity of information adjacent to the stack in the storage device, wherein the quanti... | 05/27/2008 |
| 7367022 | Methods and apparatus for optimizing the operating speed and size of a computer program Apparatus and methods for optimizing an operating speed and size of a computer program are disclosed. In an example, an apparatus includes an execution module to run a computer program, an exception detector to detect throws to an exception handler and to detect loc... | 04/29/2008 |
| 7366842 | Creating permanent storage on the fly within existing buffers A circular buffer having an active cache window can be configured to temporarily allocate one or more locations in the active cache as permanent memory locations to eliminate the possibility of overwriting the contents of the permanent memory locations. The cache wi... | 04/29/2008 |
| 7363475 | Managing registers in a processor to emulate a portion of a stack The present invention is generally directed to method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage a plurality of processor registers to store the top portion of the stack. Data is managed in these registers by managi... | 04/22/2008 |
| 7350059 | Managing stack transfers in a register-based processor The present invention is generally directed to a method and apparatus for emulating a portion of a stack. Certain embodiments of the invention manage data transfers between processor registers that are configured to emulate a top portion of a stack and memory, which... | 03/25/2008 |
| 7340592 | Executing a translated block of instructions and branching to correction code when expected top of stack does not match actual top of stack to adjust stack at execution time to continue executing without restarting translating A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a translated first block of instructions executable in a second processor arch... | 03/04/2008 |
| 7334112 | Method and apparatus for managing access to out-of-frame registers Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack includ... | 02/19/2008 |
| 7302550 | Stack of variable length operands and method for use An operand stack (10) permits optimization of memory space and a continuous check of operand type by creating a type memory (20) which stores type information for each operand, said information comprising information about the length of the operand. | 11/27/2007 |
| 7296271 | Replaceable scheduling algorithm in multitasking kernel Disclosed is providing one of a plurality of schedulers for a multitasking system for a processor that includes choosing a particular one of the schedulers, setting a program counter to an address corresponding to code of the particular one of the schedulers, and th... | 11/13/2007 |
| 7290124 | Data processor employing register banks with overflow protection to enhance interrupt processing and task switching The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception o... | 10/30/2007 |
| 7284274 | System and method for identifying and eliminating vulnerabilities in computer software applications A system and method for certifying software for essential and security-critical systems. The system and method provide a methodology and corresponding analysis engines increase the level of confidence that common vulnerabilities are not present in a particular appli... | 10/16/2007 |
| 7281123 | Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second... | 10/09/2007 |
| 7277927 | Systems and methods for saving internet content into a handheld internet appliance Systems and methods for transferring Internet content displayed on a web site in a handheld Internet appliance to a local database in the handheld Internet appliance are provided. The systems and methods of the present invention consist of a software solution that e... | 10/02/2007 |
| 7277923 | Systems and methods for automatically accessing internet information from a local application on a handheld internet appliance Systems and methods for automatically accessing Internet information and local applications from another local application on a handheld Internet appliance is provided. The systems and methods of the present invention consist of a software solution that enables user... | 10/02/2007 |
| 7272702 | Method and apparatus for managing access to out-of-frame registers Method and apparatus for managing access to registers that are outside a current register stack frame are disclosed. An instruction execution unit in a processor receives an instruction to be executed. A processor includes a register stack, the register stack includ... | 09/18/2007 |
| 7263621 | System for reducing power consumption in a microprocessor having multiple instruction decoders that are coupled to selectors receiving their own output as feedback The present disclosure illustrates a system for reducing power consumption in a computer processor. Included is a 16-bit instruction decoder for decoding instructions with 16-bit words, a 32-bit instruction decoder for decoding instructions with 32-bit words, a word... | 08/28/2007 |
| 7257665 | Branch-aware FIFO for interprocessor data sharing A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to... | 08/14/2007 |
| 7236958 | Electronic software license with software product installer identifier An anti-piracy software licensing system associates a license file with a particular software product, so that the license file cannot be used with a separate product. The license is associated with one and only one product by associating an Installer Identifier (II... | 06/26/2007 |
| 7228532 | Method and apparatus to facilitate code verification and garbage collection in a platform-independent virtual machine One embodiment of the present invention provides a system that facilitates code verification and garbage collection in a platform-independent virtual machine. The system operates by first receiving a code module written in a platform-independent language. Next, the ... | 06/05/2007 |
| 7225436 | Java hardware accelerator using microcode engine A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™... | 05/29/2007 |
| 7219335 | Method and apparatus for stack emulation during binary translation A method of monitoring processor resources. To monitor a processor resource, first a set of needed resources is determined at the beginning of a block of code. A test is then performed to determine if the set of needed resources is available at the start of the bloc... | 05/15/2007 |
| 7210027 | Processor transferring multiple working register windows transfers global registers only for select exception handling In a data processing apparatus using a register window method performing data transmission from a master register to a work register during an exception handling, detecting a trap, discriminating whether or not a data transmission is required for the global register... | 04/24/2007 |
| 7210134 | Deterring reverse-engineering of software systems by randomizing the siting of stack-based data A given software process is composed on one or more threads of execution. Each thread possesses its own stack, a region of memory set aside by the operating system for that thread to store data. Popular programming languages rely heavily on stack-based data (frequen... | 04/24/2007 |
| 7203820 | Extending a register file utilizing stack and queue techniques In a set of registers, each individually addressable by register operations using a corresponding register identification, at least one register of the set of registers is an extended register having multiple storage locations. Values stored in the multiple storage ... | 04/10/2007 |
| 7203797 | Memory management of local variables A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-... | 04/10/2007 |
| 7200736 | Method and system for substantially registerless processing A simple instruction set processor preferably utilizes six primary components: a fetch unit, and instruction and address register, a controller/decoder, an arithmetic logic unit, an address multiplexer, and a storage multiplexer. The processor utilizes a data stream... | 04/03/2007 |
| 7191313 | Microprocessor The present invention provides a microprocessor which enables task switching with a small time overhead. Upon reception of input of an interrupt control signal during execution of a task-1, a first program counter is switched to a second program counter and a first ... | 03/13/2007 |
| 7181733 | Method and apparatus for detecting an overflow condition in a kernel stack during operating system development One embodiment of the present invention provides a system with a mechanism that facilitates determining whether a kernel stack will overflow during development of an operating system. During execution of the operating system, the operating system executes a procedur... | 02/20/2007 |
| 7178002 | Methods and systems for dynamically growing multiple stacks An allocation instructions and an extension instructions allow a program to continue to execute even when the program requires more stack space than has been allocated to the program. The methods and systems thereby allow programs to run to completion in more situat... | 02/13/2007 |
| 7136990 | Fast POP operation from RAM cache using cache row value stack A method and apparatus for performing a fast pop operation from a random access cache is disclosed. The apparatus includes a stack onto which is pushed the row and way of push instruction data stored into the cache. When a pop instruction is encountered, the apparat... | 11/14/2006 |
