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| Number | Title | Issue Date |
| 8078839 | Concurrent processing element system, and method An electronic processing element is disclosed for use in a system having a plurality of processing elements. The electronic processing element includes an input instruction memory, an operation unit, and an output instruction memory. The input instruction memory is ... | 12/13/2011 |
| 7716455 | Processor with automatic scheduling of operations A high speed processor. The processor includes terminals that each execute a subset of the instruction set. In at least one of the terminals, the instructions are executed in an order determined by data flow. Instructions are loaded into the terminal in pages. A not... | 05/11/2010 |
| 7707387 | Conditional execution via content addressable memory and parallel computing execution model The use of a configuration-based execution model in conjunction with a content addressable memory (CAM) architecture provides a mechanism that enables performance of a number of computing concepts, including conditional execution, (e.g., If-Then statements and while... | 04/27/2010 |
| 7664932 | Scalable and configurable execution pipeline of handlers having policy information for selectively acting on payload Optimizing pipeline handler execution. A method may be practiced in a computing environment including an execution pipeline. The method includes acts to optimize execution of handlers in the pipeline. The method includes receiving a payload object. Policy informatio... | 02/16/2010 |
| 7613902 | Device and method for enabling efficient and flexible reconfigurable computing A power-efficient, distributed reconfigurable computing system and method are provided. A reconfigurable computing system may include an embedded controller for performing real-time control and initialization and circuitry that supports data-flow driven execution of... | 11/03/2009 |
| 7415595 | Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between ... | 08/19/2008 |
| 7409533 | Asynchronous communication among hardware object nodes in IC with receive and send ports protocol registers using temporary register bypass select for validity information Embodiments of the invention are directed to an integrated circuit including a communication network that interconnects individual object nodes. The nodes include a receiving port and a sending port, each structured to send messages along communication pathways, whi... | 08/05/2008 |
| 7406584 | IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and receiving nodes each coupled by a communication channel. Individual c... | 07/29/2008 |
| 7398329 | Pipelined I/O execution A method for pipelining execution input/output (I/O) includes obtaining a first I/O operation, determining a first plurality of stages of a pipeline needed to execute the first I/O operation, and executing each of the first plurality of stages to complete the I/O op... | 07/08/2008 |
| 7386636 | System and method for communicating command parameters between a processor and a memory flow controller A system and method for communicating command parameters between a processor and a memory flow controller are provided. The system and method make use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controlle... | 06/10/2008 |
| 7373481 | Distributed-structure-based parallel module structure and parallel processing method A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1 independent flow-sequences is created, and the N+1 flow-sequences con... | 05/13/2008 |
| 7370179 | Microprocessor The invention relates to a microprocessor having a plurality of components which are selected from registers (14,16), arithmetic logic units (30,32), memory (36,38), input/output circuits and other similar components where the plurality of compo... | 05/06/2008 |
| 7356611 | Method and apparatus for permissions based active document workflow Techniques for designing and processing a workflow that can be refined or modified based upon information associated with a document processed by the workflow. Since the author of the document may configure the information associated with a document that is used to ... | 04/08/2008 |
| 7353516 | Data flow control for adaptive integrated circuitry The present invention concerns data flow control in adaptive integrated circuitry which utilizes a data flow model for data processing. The present invention controls task initiation and execution based upon data consumption measured in data buffer units. In the var... | 04/01/2008 |
| 7337233 | Network system with TCP/IP protocol spoofing A system in which a personal computer sends messages into a TCP/IP network using a conventional dial-up link and downloads data from the TCP/IP network using a high-speed one-way satellite link. A preferred embodiment uses a conventional SLIP provider to connect to ... | 02/26/2008 |
| 7325063 | Apparatus, method, and system for removing ethernet header and adding second IP header An apparatus including a protocol stack, the protocol stack including an application layer, a network layer, and a physical layer, wherein the physical layer comprises a hardware interface between the apparatus and a network, wherein network-level tunnelling of a pa... | 01/29/2008 |
| 7318143 | Reuseable configuration data An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store opera... | 01/08/2008 |
| 7301792 | Apparatus and method of ordering state transition rules for memory efficient, programmable, pattern matching finite state machine hardware A programmable finite state machine (FSM) includes, in part, first and second memories, and a selection circuit coupled to each of the memories. Upon receiving a (k+m)-bit word representative of the k-bit input symbol and the m-bit current state, the first memory su... | 11/27/2007 |
| 7295515 | Communication network design A communication network design circuit can derive a path and a necessary link capacity for multiple point communication service permitting arbitrary communication within a predetermined range of communication amount by providing traffic amount of data in-flowing thr... | 11/13/2007 |
| 7289799 | Portable terminal apparatus and terminal apparatus A portable terminal apparatus for communicating with an external device by a cable or radio has a means for selectively sending, to the external device, an information identification code loaded from the external device by the cable or radio. ... | 10/30/2007 |
| 7287113 | Method of and apparatus for controlling bidirectional streams of isochronous data flowing between an application and a bus structure An isochronous data pipe provides a bi-directional path for data between an application and a bus structure. The isochronous data pipe includes the ability to send, receive and perform manipulations on any isochronous stream of data, including data on any number of ... | 10/23/2007 |
| 7280539 | Data driven type information processing apparatus In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a funct... | 10/09/2007 |
| 7250953 | Statistics instrumentation for low power programmable processor A graphics processor includes a graphics pipeline having a set of tap points. A configurable test point selector monitors a selected subset of tap points and counts statistics for at least one condition associated with each tap point of the subset of tap points.... | 07/31/2007 |
| 7251721 | Conditional link pointer register sets marking the beginning and end of a conditional instruction block where each set corresponds to a single stage of a pipeline that moves link pointers through each corresponding register of said register sets as instructions move through the pipeline For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one embodiment, the mechanism includes: (1) a conditional execution block state... | 07/31/2007 |
| 7249357 | Transparent distribution and execution of data in a multiprocessor environment Apparatus, methods, data structures, and systems are provided for subdividing input data associated with a first software program into job quanta, wherein each job quantum is operable to be executed by a separate software program residing on a different processing e... | 07/24/2007 |
| 7246215 | Systolic memory arrays A short latency and high bandwidth memory includes a systolic memory that is sub-divided into a plurality of memory arrays, including banks and pipelines that access these banks. Shorter latency and faster performance is achieved with this memory, because each bank ... | 07/17/2007 |
| 7243339 | System and method to decrease program analysis overhead System and method are described for program analysis with data caching. Briefly described, in architecture, the system can be implemented as follows. The present invention for program analysis with data caching includes a counter for tracking each time on of a plura... | 07/10/2007 |
| 7240347 | Systems and methods for preserving the order of data A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more ... | 07/03/2007 |
| 7237229 | Debugging aid parallel execution of a plurality of iterations with source lists display corresponding to each iteration This invention makes debugging more efficient when an object program is intended for processing a loop made up of n groups of iteration-forming instructions. Instructions in the secondary assembler program each has a combination of a line number “;lx” and an ite... | 06/26/2007 |
| 7234022 | Cache accumulator memory for performing operations on block operands Various embodiments of systems and methods for performing accumulation operations on block operands are disclosed. In one embodiment, an apparatus may include a memory, a functional unit that performs an operation on block operands, and a cache accumulator. The cach... | 06/19/2007 |
| 7228341 | Method and system for electronically distributing, displaying and controlling advertising and other communicative media A method for facilitating the electronic scheduling for playback of a variety of media such as music or video is disclosed. In the described system, discrete items of content (such as music or video) are scheduled for play back based upon a schedule created by the i... | 06/05/2007 |
| 7225319 | Digital architecture for reconfigurable computing in digital signal processing A digital embedded architecture, includes a microcontroller and a memory device, suitable for reconfigurable computing in digital signal processing and comprising: a processor, structured to implement a Very Long Instruction Word elaboration mode by a general purpos... | 05/29/2007 |
| 7206910 | Delta object replication system and method for clustered system In a clustered processing system, replication logic controls replication of objects to one or more replica states. The replication logic determines differences between states of an object. The one or more replica states can then be generated on other nodes in the cl... | 04/17/2007 |
| 7203818 | Microcontroller instruction set A microcontroller apparatus is provided with an instruction set for manipulating the behavior of the microcontroller. The apparatus and system is provided that enables a linearized address space that makes modular emulation possible. Direct or indirect addressing is... | 04/10/2007 |
| 7187650 | Fibre channel frame-mode GFP with distributed delimiter A technique for providing multiple Fibre Channel frames in one frame-mapped GFP transport frame. GFP conventions are followed, except that a Distributed Delimiter marks each Fibre Channel frame in the payload of GFP transport frame. The Distributed Delimiter has a F... | 03/06/2007 |
| 7177877 | Method and system for externalizing conditional logic for collecting multi-purpose objects A method and system for externalizing conditional logic for an integrated programming architecture provides a static tree structure traversed by a dynamic object collector. The tree structure includes a plurality of conditional nodes and a plurality of branches for ... | 02/13/2007 |
| 7174525 | Integrated structure layout and layout of interconnections for an instruction execution unit of an integrated circuit chip An integrated structure layout of functional blocks and interconnections for an integrated circuit chip. Data dependency comparator blocks are arranged in rows and columns. This arrangement defines layout regions between adjacent ones of the data dependency comparat... | 02/06/2007 |
| 7168065 | Method for monitoring program flow to verify execution of proper instructions by a processor In a method for monitoring the flow of execution of a series of instructions of a computer program, a sequence of instructions are transmitted to the processor to execute the monitored program. These instructions are analyzed, and the result of the analysis are veri... | 01/23/2007 |
| 7152221 | External resource files for application development and management A method and system are provided for efficient development of software application programs with user interfaces. Customarily, several specialists, including designers and developers, cooperate during the development stage of an application program. The invention te... | 12/19/2006 |
| 7145921 | Asynchronous data pipe for automatically managing asynchronous data transfers between an application and a bus structure An asynchronous data pipe (ADP) automatically generates transactions necessary to complete asynchronous data transfer operations for an application over a bus structure. The ADP includes a register file which is programmed and initiated by the application. The regis... | 12/05/2006 |
