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| Number | Title | Issue Date |
| 8181000 | Method and apparatus for binding shadow registers to vectored interrupts A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond... | 05/15/2012 |
| 7934076 | System and method for limiting exposure of hardware failure information for a secured execution environment A method and apparatus for limiting the exposure of hardware failure information is described. In one embodiment, an error reporting system of a processor may log various status and error address data into registers that retain their contents through a warm reset ev... | 04/26/2011 |
| 7930520 | Processor and program execution method capable of efficient program execution A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select ... | 04/19/2011 |
| 7925864 | Method and apparatus for binding shadow registers to vectored interrupts A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond... | 04/12/2011 |
| 7870366 | Chained operation of functional components with DONE and GO registers storing memory address for writing and reading linking signal value The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to per... | 01/11/2011 |
| 7822947 | Aliasing data processing registers A register data store 20 is provided within a data processing system 2. The register data store 20 may be accessed via registers for which a data processing instruction specifies a register size Q, D and a data element size S16, S8... | 10/26/2010 |
| 7761688 | Multiple thread in-order issue in-order completion DSP and micro-controller An in-order issue in-order completion micro-controller comprises a pipeline core comprising in succession a fetch address stage, a program access stage, a decode stage, a first execution stage, a second execution stage, a memory access stage, and a write back stage.... | 07/20/2010 |
| 7761689 | Programming a digital processor with a single connection A digital processor is coupled to a processor programmer through a single programming connection (e.g., terminal, pin, etc.) coupled to the single conductor programming bus. The processor programmer comprises an instruction encoder/decoder, a Manchester encoder, a M... | 07/20/2010 |
| 7757065 | Instruction segment recording scheme In a front-end system for a processor, a recording scheme for instruction segments stores the instructions in reverse program order. Instruction segments may be traces, extended blocks or basic blocks. By storing the instructions in reverse program order, the instru... | 07/13/2010 |
| 7694109 | Data processing apparatus of high speed process using memory of low speed and low power consumption When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory... | 04/06/2010 |
| 7647476 | Common analog interface for multiple processor cores In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via... | 01/12/2010 |
| 7584343 | Data reordering processor and method for use in an active memory device An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses,... | 09/01/2009 |
| 7500084 | Multifunction hexadecimal instruction form A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructi... | 03/03/2009 |
| 7487331 | Programming a digital processor with a single connection A digital processor may be coupled to a processor programmer through a single conductor programming bus. The digital processor and the processor programmer, each may have a single programming connection (e.g., terminal, pin, etc.) coupled to the single conductor pro... | 02/03/2009 |
| 7487332 | Method and apparatus for binding shadow registers to vectored interrupts A method and apparatus within a processing system is provided for associating shadow register sets with interrupt routines. The invention includes a vector generator that receives interrupts, and generates exception vectors to call interrupt routines that correspond... | 02/03/2009 |
| 7478223 | Symbol parsing architecture A devices and method for parsing a data stream comprises a parser stack configured to store one or more parsing symbols, each parsing symbol representing a different state of data stream parsing, a table interface configured to retrieve one or more production rules ... | 01/13/2009 |
| 7464252 | Programmable processor and system for partitioned floating-point multiply-add operation A programmable processor and system for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable... | 12/09/2008 |
| 7444488 | Method and programmable unit for bit field shifting A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first memory unit to a second memory unit, are presented. The bit segment is ... | 10/28/2008 |
| 7437536 | Systems and methods for task migration Methods and systems are provided whereby, in one aspect, pointers to address locations of instructions, static data and dynamically-created data are stored such that the instructions, static data and dynamically-created data can be moved to a different memory or pro... | 10/14/2008 |
| 7434028 | Hardware stack having entries with a data portion and associated counter According to some embodiments, determining a new value to be pushed onto a hardware stack having n entries is determined. Each entry in the stack may include a data portion and an associated counter. If the new value equals the data portion of the entry associated w... | 10/07/2008 |
| RE40509 | Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture An improved manifold array (ManArray) architecture addresses the problem of configurable application-spacific instruction set optimization and instruction memory reduction using an instruction abbreviation process thereby further optimizing the general ManArray arch... | 09/16/2008 |
| 7415596 | Parser table/production rule table configuration using CAM and SRAM A system and method for parsing a data stream comprises a production rule table populated with production rules, a parser table populated with production rule codes that correspond to production rules within the production rule table, and a direct execution parser t... | 08/19/2008 |
| 7415042 | System and method for dynamic information retrieval using a state machine A system and method for retrieving information from a frame. A plurality of entries is initialized in a translation table. The translation table has a plurality of rows. Each of the plurality of rows represents a state. The rows have a plurality of entries. Each of ... | 08/19/2008 |
| 7409532 | Method and apparatus for extending operations of an application in a data processing system A method, an apparatus, and computer instructions are provided for extending operations of an application in a data processing system. A primary operation is executed. All extended operations of the primary operation are cached and pre and post operation identifiers... | 08/05/2008 |
| 7406584 | IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and receiving nodes each coupled by a communication channel. Individual c... | 07/29/2008 |
| 7403835 | Device and method for programming an industrial robot In a device and method for programming an industrial robot using a simulation program, control commands are issued by a handheld programming device and these commands are visualized on an image surface as movement and/or processing operations by the robot on the bas... | 07/22/2008 |
| 7398276 | Parallel predictive compression and access of a sequential list of executable instructions Compression and decompression of data such as a sequential list of executable instructions (e.g., program binaries) by uniformly applying a predictive model generated from one segment of the executable list as a common predictive starting point for the other segment... | 07/08/2008 |
| 7395082 | Method and system for handling events in an application framework for a wireless device Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI wireless framework. An identity of the acquired MMI event may be deter... | 07/01/2008 |
| 7395411 | Methods and apparatus for improving processing performance by controlling latch points Methods and apparatus provide for performing pre-execution processes to prepare instructions of an instruction set for further processing; executing the instructions in a pipeline of execution stages using digital logic for processing data in accordance with the ins... | 07/01/2008 |
| 7392344 | Data-processing system and method for supporting varying sizes of cache memory A data-processing system and method include a processor core associated with a cache controller. A plurality of cached memory components is associated with the processor core and the cache controller. A cached processor is provided, which supports a plurality of var... | 06/24/2008 |
| 7383425 | Massively reduced instruction set processor This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to process IP packets for video communications and control of the video... | 06/03/2008 |
| 7380105 | Prediction based instruction steering to wide or narrow integer cluster and narrow address generation A method and apparatus for improving the operation of a computer processor by utilizing an asymmetric clustered processor architecture are disclosed. The asymmetric clustered processor apparatus includes a narrow cluster, a wide cluster, a steering logic utilizing a... | 05/27/2008 |
| 7376807 | Data processing system having address translation bypass and method therefor In a data processing system a processor including processing logic performs data processing. An address translator that is coupled to the processing logic performs address translation and a method thereof. The address translator receives a logical address and conver... | 05/20/2008 |
| 7373143 | Adaptive radio patch interface system The present invention is directed to an RF communications system that includes a first radio processor module having a first receiver portion programmed to convert a first analog receive signal into a first digital audio receive signal. The first analog receive sign... | 05/13/2008 |
| 7370181 | Single stepping a virtual machine guest using a reorder buffer Embodiments of apparatuses, systems, and methods for single stepping a virtual machine guest using a reorder buffer are disclosed. In one embodiment, an apparatus includes a sequencer and a reorder buffer. The sequencer is to issue micro-operations. The reorder buff... | 05/06/2008 |
| 7370243 | Precise error handling in a fine grain multithreaded multicore processor A method and mechanism for error recovery in a processor. A multithreaded processor is configured to utilize software for hardware detected machine errors. Rather than correcting and clearing the detected errors, hardware is configured to report the errors precisely... | 05/06/2008 |
| 7370183 | Branch predictor comprising a split branch history shift register An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch within a second operating context, such as an operating system conte... | 05/06/2008 |
| 7366829 | TLB tag parity checking without CAM read An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need to read a CAM entry from a TLB during a TLB access by storing the tag ... | 04/29/2008 |
| 7363469 | Method and system for on-demand scratch register renaming A method and processor for performing on-demand scratch register reallocation by dynamically adjusting the number of scratch registers from within the pool of rename registers includes initially allocating from a set of physical registers one or more architected reg... | 04/22/2008 |
| 7360205 | Minimizing interaction costs among components of computer programs A system and method for minimizing total cost of interaction among components of a computer program which are each characterized by at least one implementation property. A implementation property may, for example, be a choice of string representation (e.g. ASCII, UN... | 04/15/2008 |
