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| Number | Title | Issue Date |
| 8190856 | Data transfer network and control apparatus for a system with an array of processing elements each either self- or common controlled A processor of SIMD/MIMD dual mode architecture comprises common controlled first processing elements, self-controlled second processing elements and a pipelined (ring) network connecting the first PEs and the second PEs sequentially. An access controller has access... | 05/29/2012 |
| 8180998 | System of lanes of processing units receiving instructions via shared memory units for data-parallel or task-parallel operations A system for performing data-parallel operations and task-parallel operations. A first switch fabric node (SFN) includes first and second lane processing engines (LPEs). The first LPE includes a first set of lane processing units (LPUs) configured to perform data-pa... | 05/15/2012 |
| 8112613 | Selecting broadcast SIMD instruction or cached MIMD instruction stored in local memory of one of plurality of processing elements for all elements in each unit Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, whic... | 02/07/2012 |
| 8103854 | Methods and apparatus for independent processor node operations in a SIMD array processor A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pau... | 01/24/2012 |
| 7979674 | Re-executing launcher program upon termination of launched programs in MIMD mode booted SIMD partitions Executing MIMD programs on a SIMD machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the compute nodes initially configured exclusively for SIMD operations, the SIMD machine fur... | 07/12/2011 |
| 7853775 | Processing elements grouped in MIMD sets each operating in SIMD mode by controlling memory portion as instruction cache and GPR portion as tag Disclosed is a mixed mode parallel processor system in which N number of processing elements PEs, capable of performing SIMD operation, are grouped into M (=N÷S) processing units PUs performing MIMD operation. In MIMD operation, P out of S memories in each PU, whic... | 12/14/2010 |
| 7831803 | Executing multiple instructions multiple date (‘MIMD’) programs on a single instruction multiple data (‘SIMD’) machine Executing MIMD programs on a SIMD machine, including establishing on the SIMD machine a plurality of SIMD partitions; booting a first SIMD partition in MIMD mode; executing, on a compute node of the first SIMD partition booted in MIMD mode, a MIMD accelerator progra... | 11/09/2010 |
| 7831802 | Executing Multiple Instructions Multiple Data (‘MIMD’) programs on a Single Instruction Multiple Data (‘SIMD’) machine Executing Multiple Instructions Multiple Data (‘MIMD’) programs on a Single Instruction Multiple Data (‘SIMD’) machine, the SIMD machine including a plurality of compute nodes, each compute node capable of executing only a single thread of execution, the com... | 11/09/2010 |
| 7831804 | Multidimensional processor architecture A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which each include at least one microprocessor block having a computational p... | 11/09/2010 |
| 7818539 | System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be proce... | 10/19/2010 |
| 7814295 | Moving processing operations from one MIMD booted SIMD partition to another to enlarge a SIMD partition Executing MIMD programs on a SIMD machine, including establishing SIMD partitions on the SIMD machine; booting SIMD partitions in MIMD mode; executing MIMD programs on the compute nodes of a first SIMD partition booted in MIMD mode; re-executing a launcher program b... | 10/12/2010 |
| 7814296 | Arithmetic units responsive to common control signal to generate signals to selectors for selecting instructions from among respective program memories for SIMD / MIMD processing control Provided is a data processing circuit. A control unit outputs an operation control signal and a memory control signal. A plurality of program memories each outputs a command in response to the memory control signal. A plurality of arithmetic sections each selectivel... | 10/12/2010 |
| 7730280 | Methods and apparatus for independent processor node operations in a SIMD array processor A control processor is used for fetching and distributing single instruction multiple data (SIMD) instructions to a plurality of processing elements (PEs). One of the SIMD instructions is a thread start (Tstart) instruction, which causes the control processor to pau... | 06/01/2010 |
| 7441098 | Conditional execution of instructions in a computer A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of t... | 10/21/2008 |
| 7418575 | Long instruction word processing with instruction extensions A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of computational instructions and long instruction word instructions with ... | 08/26/2008 |
| 7404066 | Active memory command engine and method A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also g... | 07/22/2008 |
| 7401333 | Array of parallel programmable processing engines and deterministic method of operating the same The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least some threads communicate with each other through communication objects e... | 07/15/2008 |
| 7392329 | System and method for applying an action initiated for a portion of a plurality of devices to all of the plurality of devices In accordance with one embodiment of the present invention, a method of applying an action initiated for a portion of a plurality of devices to all of the plurality of devices is provided. The method comprises establishing a status block for a plurality of devices t... | 06/24/2008 |
| 7383427 | Multi-scalar extension for SIMD instruction set processors A method is provided for executing a plurality of parallel executable sequences of instructions on a processor having a plurality of execution units operated by a single instruction unit. The method includes a) detecting a plurality of sequences of instructions adap... | 06/03/2008 |
| 7373490 | Emptying packed data state during execution of packed data instructions A method in a computer system, one embodiment includes accessing a packed data instruction and generating a corresponding set of control bits to cause a processor to alter a top of stack to zero of a programmer visible register file, accessing a floating point instr... | 05/13/2008 |
| 7367021 | Method and apparatus for generating multiple processor-specific code segments in a single executable A computer-implemented method analyzes a source code segment which is to be compiled for execution by any one of several different processor types. The method determines whether a performance advantage would be achieved by generating a customized version of object c... | 04/29/2008 |
| 7363620 | Non-linear execution of application program instructions for application program obfuscation Obfuscating an application program comprises reading a first application program, determining an application program instruction location permutation that transforms the first application program into an obfuscated application program having at least one application... | 04/22/2008 |
| 7360005 | Software programmable multiple function integrated circuit module An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable func... | 04/15/2008 |
| 7356670 | Data processing system A multiprocessor data processing system is described wherein the processors communicate to each other via a shared memory. Each of the processors comprises an administration unit (18a) and a computational unit. The administration unit of a writing proc... | 04/08/2008 |
| 7353499 | Multiple instruction dispatch tables for application program obfuscation Obfuscating an application program comprises reading an application program comprising code, determining multiple dispatch tables associated with the application program, transforming the application program into application program code configured to utilize the di... | 04/01/2008 |
| 7350057 | Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an ins... | 03/25/2008 |
| 7350054 | Processor having array of processing elements whose individual operations and mutual connections are variable An arrayed processor has a plurality of processing elements each having a plurality of types of arithmetic logic units for processing data having different numbers of bits from one another. The arrayed processor divides a series of processing data of various numbers... | 03/25/2008 |
| 7343475 | Supplying halt signal to data processing unit from integer unit upon single unit format instruction in system capable of executing double unit format instruction A processor including an integer processing unit and a data processing unit. The processor can be operated by a first instruction format or a second instruction format. The first instruction format includes only an instruction for the integer processing unit, and is... | 03/11/2008 |
| 7335965 | Packaging of electronic chips with air-bridge structures A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structur... | 02/26/2008 |
| 7328235 | Multiple processing method A multiprocessing method suitable for realizing satisfactory online processing by synchronizing data processing in respective element processor nodes in spite of a loosely coupled system used with the plural element processor nodes driven with individual clocks, the... | 02/05/2008 |
| 7320065 | Multithread embedded processor with input/output capability An embedded processor system having a single-chip embedded microprocessor with analog and digital electrical interfaces to external systems. A novel processor core uses pipelined execution of multiple independent or dependent concurrent threads, together with superv... | 01/15/2008 |
| 7313646 | Interfacing of functional modules in an on-chip system An electronic system comprises an initiator module and a target module addressable by the initiator module, and an interface and control module for interfacing between respective communication protocols of the initiator module and of the target module. The interface... | 12/25/2007 |
| 7313671 | Processing apparatus, processing method and compiler Computer architectures consist of a fixed data path, which is controlled by a set of control words. Each control word controls part of the data path. Each set of instructions generates a new set of control words. In case of a VLIW processor, multiple instructions ar... | 12/25/2007 |
| 7285487 | Method and apparatus for network with multilayer metalization A network for interconnecting processing element nodes which supports rich interconnection while having a number of switching elements which is linear in the number of processing elements interconnected. Processing elements connect to the lowest level of the tree an... | 10/23/2007 |
| 7287185 | Architectural support for selective use of high-reliability mode in a computer system In one aspect of the present invention, a circuit is provided which implements an instruction set architecture defining a first instruction group, a second instruction group to enter a high-reliability mode of operation, and a third instruction group to enter a non-... | 10/23/2007 |
| 7249247 | Common feature mode for microprocessors in a multiple microprocessor system A mechanism whereby a set of microprocessors may be set to a common mode in which the microprocessors utilize one or more features that are common to all microprocessors. The common mode facilitates proper multiprocessor operation and permits a fix (e.g., a microcod... | 07/24/2007 |
| 7237099 | Multiprocessor system having a plurality of control programs stored in a continuous range of addresses of a common memory and having identification registers each corresponding to a processor and containing data used in deriving a starting address of a CPU-linked interrupt handler program to be executed by the corresponding processor A multiprocessor system has a plurality of CPUs with respective local buses, and a memory which stores a plurality of programs to be executed by the CPUs and is connected to a common bus which can be accessed via the local buses, each local bus being connected to a ... | 06/26/2007 |
| 7233998 | Computer architecture and software cells for broadband networks A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a contro... | 06/19/2007 |
| 7234018 | Layered crossbar for interconnection of multiple processors and shared memories A method and apparatus includes a plurality of processor groups each having a plurality of processor switch chips each having a plurality of processors and a processor crossbar, each processor connected to the processor crossbar; a plurality of switch groups each ha... | 06/19/2007 |
| 7234029 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculativ... | 06/19/2007 |
