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| Number | Title | Issue Date |
| 7865693 | Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type Mechanisms for aligning enhanced precision vectors based on reduced precision data values are provided. At least one data value, having a first precision type, is received for storing in a vector register. The vector register stores data as a vector having a plurali... | 01/04/2011 |
| 7676647 | System and method of processing data using scalar/vector instructions A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation ... | 03/09/2010 |
| 7526629 | Vector processing apparatus with overtaking function to change instruction execution order A vector processing apparatus includes a main memory, an instruction issuing section which issues instructions, an overtaking control circuit which outputs the instructions received from the instruction issuing section to an instruction executing section in an order... | 04/28/2009 |
| 7467286 | Executing partial-width packed data instructions A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the registers, a decoder coupled to the register renaming unit, and a partial-wi... | 12/16/2008 |
| 7457938 | Staggered execution stack for vector processing In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and executing the operation on high order portions of the first and second so... | 11/25/2008 |
| 7418574 | Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively,... | 08/26/2008 |
| 7404065 | Flow optimization and prediction for VSSE memory operations In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises generating an optimized micro-operation (μop) flow for an instructio... | 07/22/2008 |
| 7366032 | Multi-ported register cell with randomly accessible history A multi-ported register cell. The register cell includes a base cell and a plurality of history cells, each of which is coupled to the base cell. Each of the plurality history cells is coupled to write to the base cell through a first port, and each of the plurality... | 04/29/2008 |
| 7367026 | Framework for integrated intra- and inter-loop aggregation of contiguous memory accesses for SIMD vectorization A method, computer program product, and information handling system for generating loop code to execute on Single-Instruction Multiple-Datapath (SIMD) architectures, where the loop contains multiple non-stride-one memory accesses that operate over a contiguous strea... | 04/29/2008 |
| 7356710 | Security message authentication control instruction A method, system and computer program product for computing a message authentication code for data in storage of a computing environment. An instruction specifies a unit of storage for which an authentication code is to be computed. An computing operation computes a... | 04/08/2008 |
| 7353367 | System and software for catenated group shift instruction A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the e... | 04/01/2008 |
| 7353149 | Method and apparatus for simulating dynamic contact of objects Contact of rigid bodies is simulated with friction. A contact point is determined as a mid point between closest points on each body. An integrated relative velocity (IRV) vector is computed, and is minimized by applying forces to both bodies. If the IRV value excee... | 04/01/2008 |
| 7328289 | Communication between processors A method of communicating between a first and a second processor includes the first processor sending a datum over a common control bus, and the second processor receiving the datum from the common control bus. ... | 02/05/2008 |
| 7275147 | Method and apparatus for data alignment and parsing in SIMD computer architecture Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a shift value, preferably as parameters of the instruction. A first and... | 09/25/2007 |
| 7263692 | System and method for software-pipelining of loops with sparse matrix routines A method that uses software-pipelining to translate programs, from higher level languages into equivalent object or machine language code for execution on a computer, including sparse arrays/matrices. In one example embodiment, this is accomplished by transforming s... | 08/28/2007 |
| 7260708 | Programmable processor and method for partitioned group shift A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a shift amount and a register containing a plurality of data elements, wherein the e... | 08/21/2007 |
| 7257718 | Cipher message assist instructions A method, system and program product for enciphering or deciphering storage of a computing environment by specifying, via an instruction, a unit of storage to be enciphered or deciphered. The unit of storage to be enciphered or deciphered includes a plurality of pag... | 08/14/2007 |
| 7257695 | Register file regions for a processing system According to some embodiments, a dynamic region in a register file may be described for an operand. The described region may, for example, store multiple data elements, each data element being associated with an execution channel of an execution engine. Information ... | 08/14/2007 |
| 7230633 | Method and apparatus for image blending Methods and apparatuses for blending two images using vector table look up operations. In one aspect of the invention, a method to blend two images includes: loading a vector of keys into a vector register; converting the vector of keys into a first vector of blendi... | 06/12/2007 |
| 7222225 | Programmable processor and method for matched aligned and unaligned storage instructions A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions in an instruction set comprising (a) group instructions that operate on a plurality of data elements... | 05/22/2007 |
| 7216217 | Programmable processor with group floating-point operations A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to ret... | 05/08/2007 |
| 7209482 | Reorder engine with error recovery A reorder engine classifies information relating to incoming data items as belonging to either a first, second, or third region. The information relating to the data items may arrive at the reorder engine out of order. The data items each include a sequence number t... | 04/24/2007 |
| 7209591 | Motion compensation method for video sequence encoding in low bit rate systems A method for motion accounting and compensation while encoding allows improvement of the restored image quality. Image is a predicted frame in video sequence. Motion compensation is understood as an error residual signal compressing scheme, executed during video seq... | 04/24/2007 |
| 7206857 | Method and apparatus for a network processor having an architecture that supports burst writes and/or reads A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth of information from an input RAM that implements the input queue. The ... | 04/17/2007 |
| 7197625 | Alignment and ordering of vector elements for single instruction multiple data processing The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit int... | 03/27/2007 |
| 7197623 | Multiple processor cellular radio Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The Protocol Processor comprises a program part (30) including an incrementation registe... | 03/27/2007 |
| 7197606 | Information storing method for computer system including a plurality of computers and storage system A computer 10a stores boot information OA1 and application information AP1 stored on a local disk 16a, the information being respectively stored as an OS1 shared file group in a shared LU1 and as a AP1 s... | 03/27/2007 |
| 7167972 | Vector/scalar system with vector unit producing scalar result from vector results according to modifier in vector instruction Described herein is a processor for executing instructions and a method therefor. The processor comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value ... | 01/23/2007 |
| 7159122 | Message digest instructions A method, system and computer program product for digesting data in storage of a computing environment. The digesting computes a condensed representation of a message or data stored in the computer storage. A COMPUTE INTERMEDIATE MESSAGE DIGEST (KIMD) and a COMPUTE ... | 01/02/2007 |
| 7159099 | Streaming vector processor with reconfigurable interconnection switch A re-configurable, streaming vector processor (100) is provided which includes a number of function units (102), each having one or more inputs for receiving data values and an output for providing a data value, a re-configurable interconnection switch... | 01/02/2007 |
| 7155601 | Multi-element operand sub-portion shuffle instruction execution An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one embodiment, one of the data elements in the upper half of the data operand is s... | 12/26/2006 |
| 7149877 | Byte execution unit for carrying out byte instructions in a processor A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a coun... | 12/12/2006 |
| 7149875 | Data reordering processor and method for use in an active memory device An active memory device includes a command engine that receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses,... | 12/12/2006 |
| 7146486 | SIMD processor with scalar arithmetic logic units A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different data item, where each different time interval is one of a plurality ... | 12/05/2006 |
| 7127594 | Multiprocessor system and program optimizing method A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information indicating the program control mode, a VLIW mode or a multithread mode, in a p... | 10/24/2006 |
| 7107436 | Conditional next portion transferring of data stream to or from register based on subsequent instruction aspect Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of elements to be transferred to or from memory, and an rcnt parameter may be... | 09/12/2006 |
| 7096399 | Monitoring packet content A method includes, producing in an engine thread included in a processor that processes packets, a vector that represents content of a packet, and storing the vector in a memory associated with the processor such that the vector is accessible by another engine threa... | 08/22/2006 |
| 7071736 | Half-swing line precharge method and apparatus A method and apparatus of precharging data and/or address lines each having a large number of loads to a voltage midway between high and low using a source-follower configuration, and optionally driving only one-half of the precharge circuit based on a previous logi... | 07/04/2006 |
| 7058793 | Pipeline controller for providing independent execution between the preliminary and advanced stages of a synchronous pipeline A synchronous pipeline design is provided that includes a first predetermined number of fetch logic sections, or “stages”, and a second predetermined number of execution stages. Instructions are retrieved from memory and undergo instruction pre-decode and decode... | 06/06/2006 |
| 7054964 | Method and system for bit-based data access A system and a method for transcoding multiple media channels are provided. The system includes a first processor to parse a media data stream having one or more media data channels and a vector processor to decompress, scale, and then compress the parsed media chan... | 05/30/2006 |
