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| Number | Title | Issue Date |
| 7979673 | Method and apparatus for matrix decompositions in programmable logic devices A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation b... | 07/12/2011 |
| 7418536 | Processor having systolic array pipeline for processing data packets A processor for use in a router, the processor having a systolic array pipeline for processing data packets to determine to which output port of the router the data packet should be routed. In one embodiment, the systolic array pipeline includes a plurality of progr... | 08/26/2008 |
| 7380101 | Architecture for a processor complex of an arrayed pipelined processing engine A processor complex architecture facilitates accurate passing of transient data among processor complex stages of a pipelined processing engine. The processor complex comprises a central processing unit (CPU) coupled to an instruction memory and a pair of context da... | 05/27/2008 |
| 7373547 | Self-reparable semiconductor and method thereof A self-reparable semiconductor comprises first, second and spare functional units including first and second sub-functional units that cooperate to perform first and second functions. The first and second sub-functional units of the first, second and first spare fun... | 05/13/2008 |
| 7363566 | Pattern generator and test apparatus There is provided a pattern generator that generates a test pattern for testing an electronic device using test data previously supplied. The pattern generator includes a cache memory, a main memory operable to store a plurality of test data blocks of which each blo... | 04/22/2008 |
| 7343362 | Low complexity classification from a single unattended ground sensor node Disclosed are a system and method of multi-modality sensor data classification and fusion comprising partitioning data stored in a read only memory unit on a sensor node using a low query complexity boundary-decision classifier, applying an iterative two-dimensional... | 03/11/2008 |
| 7340644 | Self-reparable semiconductor and method thereof A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a def... | 03/04/2008 |
| 7328270 | Communication protocol processor having multiple microprocessor cores connected in series and dynamically reprogrammed during operation via instructions transmitted along the same data paths used to convey communication data A communication protocol processor is presented including a transmit unit and a receive unit, each having multiple microprocessor cores connected in series. Each microprocessor core performs an operation upon a stream of communication data, conducted along a data pa... | 02/05/2008 |
| 7313723 | Self-reparable semiconductor and method thereof A self-reparable semiconductor comprises first and second physical layer devices each including first and second subfunctional units that cooperate to provide first and second ports associated with a multi-bit Gigabit physical layer device. A first spare physical la... | 12/25/2007 |
| 7283528 | On the fly header checksum processing using dedicated logic A packet header processing engine includes a packet processing unit that is configured to generate the packet header information based on the packet header data. A checksum generating unit is connected to the packet processing unit. The checksum generating unit is c... | 10/16/2007 |
| 7281093 | Memory apparatus for a message processing system and method of providing same Memory apparatus for a message processing system and method of providing the same is described. In one example, a message processing system (200) includes a set of n processing elements (202) for processing messages, where n is an integer greater than ... | 10/09/2007 |
| 7278009 | Tiered sequential processing media data through multiple processor chains with longest path tier assignment of processors Tiered command distribution is described. In an embodiment, a pipeline architecture includes processor chains of data processors that process control events received from an application interface control. A tier assignment algorithm determines the longest path of da... | 10/02/2007 |
| 7274706 | Methods and systems for processing network data Methods and systems for processing data communicated over a network. In one aspect, an exemplary embodiment includes processing a first group of network packets in a first processor which executes a first network protocol stack, where the first group of network pack... | 09/25/2007 |
| 7266407 | Multi-frequency microwave-induced thermoacoustic imaging of biological tissue A method and system for examining biological tissue includes the steps of radiating a tissue region with a plurality of microwave radiation pulses. The microwave pulses are swept across a range of microwave frequencies. In response to the swept frequency microwave p... | 09/04/2007 |
| 7260709 | Processing method and apparatus for implementing systolic arrays The present invention relates to a processing method and apparatus for implementing a systolic-array-like structure. Input data are stored in a depth-configurable register means (DCF) in a predetermined sequence, and are supplied to a processing means (FU) for proce... | 08/21/2007 |
| 7251720 | Flexible digital signal processor The invention describes a digital signal processor to execute at least one dedicated operation of a dedicated system such as an digital front-end of any digital subscriber line system. The digital signal processor is a flexible digital signal processor and comprises... | 07/31/2007 |
| 7249270 | Method and apparatus for placing at least one processor into a power saving mode when another processor has access to a shared resource and exiting the power saving mode upon notification that the shared resource is no longer required by the other processor The present invention provides a data processing apparatus and method of controlling access to a shared resource. The data processing apparatus has a plurality of processors operable to perform respective data processing operations requiring access to the shared res... | 07/24/2007 |
| 7240347 | Systems and methods for preserving the order of data A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more ... | 07/03/2007 |
| 7239630 | Dedicated processing resources for packet header generation A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit may include a single execution sect... | 07/03/2007 |
| 7237086 | Configuring a management module through a graphical user interface for use in a computer system A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the customization program to customize the baseboard management controller based ... | 06/26/2007 |
| 7237036 | Fast-path apparatus for receiving data corresponding a TCP connection A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packe... | 06/26/2007 |
| 7236501 | Systems and methods for handling packet fragmentation A packet header processing engine receives a header of a packet. The received header includes a size of the packet. A maximum transfer unit size of a destination interface of the packet may be determined. The packet header processing engine determines whether the si... | 06/26/2007 |
| 7234029 | Method and apparatus for reducing memory latency in a cache coherent multi-node architecture A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a cache coherence protocol are determined. The home node initiates a read to memory to complete the speculativ... | 06/19/2007 |
| 7218632 | Packet processing engine architecture The invention provides a method and system for packet processing, in which a router (or switch) is capable of quickly processing incoming packets, thus performing level 2, 3, and 4 routing and additional services, in real time. A system includes a packet processing ... | 05/15/2007 |
| 7218906 | Layered space time processing in a multiple antenna system A system and method for performing extended space-time processing. An improved symbol decision is generated of a desired sub-channel of the signal vector by first generating a baseline decision for the sub-channel. A contribution of a strongest sub-channel is subtra... | 05/15/2007 |
| 7215662 | Logical separation and accessing of descriptor memories A packet header processing engine includes a memory having a number of distinct portions for respectively storing different types of descriptor information for a header of a packet. A packet header processing unit includes a number of pointers corresponding to the n... | 05/08/2007 |
| 7212530 | Optimized buffer loading for packet header processing A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a f... | 05/01/2007 |
| 7212959 | Method and apparatus for accumulating floating point values A method and apparatus for accumulating arbitrary length strings of input values, such as floating point values, in a layered tree structure such that the order of adds at each layer is maintained. The accumulating utilizes a shared adder, and includes means for dir... | 05/01/2007 |
| 7191342 | Methods and circuits for allowing encrypted and unencrypted configuration data to share configuration frames Described are methods and circuits that allow encrypted and unencrypted, or differently encrypted, configuration data to define the contents of the same physical memory frame or frames within a programmable logic device. ... | 03/13/2007 |
| 7185225 | Self-reparable semiconductor and method thereof A self-reparable semiconductor includes multiple functional units that perform the same function and that include sub-functional units. The semiconductor includes one or more full or partial spare functional units that are integrated into the semiconductor. If a def... | 02/27/2007 |
| 7180893 | Parallel layer 2 and layer 3 processing components in a network router A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a f... | 02/20/2007 |
| 7158520 | Mailbox registers for synchronizing header processing execution A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. Mailbox registers allow the L2 and L3 header generation un... | 01/02/2007 |
| 7159059 | Ultra-modular processor in lattice topology A Modular Operating Topology Element (MOTE), within a software-latticed network, implements ultra-concurrent operation of a plurality of such MOTEs, as single miniaturized packages, e.g., Compact Flash, each with a full function processor (CPU), a unique resident op... | 01/02/2007 |
| 7146486 | SIMD processor with scalar arithmetic logic units A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different data item, where each different time interval is one of a plurality ... | 12/05/2006 |
| 7139836 | One-way transaction tagging in a switch crossbar A method and computer program product includes, at a sender, identifying a forward item including a transmit portion and a retain portion, generating a tag, associating the tag with the retain portion, sending the transmit portion, but not the tag, to a target; at t... | 11/21/2006 |
| 7120658 | Digital systolic array architecture and method for computing the discrete Fourier transform A more computationally efficient and scalable systolic architecture is provided for computing the discrete Fourier transform. The systolic architecture also provides a method for reducing the array area by limiting the number of complex multipliers. In one embodimen... | 10/10/2006 |
| 7100020 | Digital communications processor An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue m... | 08/29/2006 |
| 7100021 | Barrier synchronization mechanism for processors of a systolic array A mechanism synchronizes among processors of a processing engine in an intermediate network station. The processing engine is configured as a systolic array having a plurality of processors arrayed as rows and columns. The mechanism comprises a barrier synchronizati... | 08/29/2006 |
| 7089407 | Packet processing device processing input packet data in a packet routing device A packet processing device which can reserve a calculation time for each instruction procedure execution unit independent of the data length of a packet by sequentially selecting an instruction procedure execution unit by a selection signal generation unit and perfo... | 08/08/2006 |
| 7082419 | Neural processing element for use in a neural network A neural processing element for use in a modular neural network is provided. One embodiment provides a neural network comprising an array of autonomous modules (300). The modules (300) can be arranged in a variety of configurations to form neural netwo... | 07/25/2006 |
