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| Number | Title | Issue Date |
| 8145881 | Data processing device and method A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second cloc... | 03/27/2012 |
| 8055881 | Computing nodes for executing groups of instructions A computation node according to various embodiments of the invention includes at least one input port capable of being coupled to at least one first other 5 computation node, a first store coupled to the input port(s) to store input data, a second store to receive a... | 11/08/2011 |
| 7996652 | Processor architecture with switch matrices for transferring data along buses A processor architecture includes a plurality of elements arranged in an array of rows and columns and a plurality of first and second bus pairs with the first pair being located between different adjacent rows of the array and having first and second buses running ... | 08/09/2011 |
| 7844796 | Data processing device and method A data processing device comprising a multidimensional array of coarse grained logic elements processing data and operating at a first clock rate and communicating with one another and/or other elements via busses and/or communication lines operated at a second cloc... | 11/30/2010 |
| 7653804 | Resource sharing in multiple parallel pipelines A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks are each coupled to receive control signaling and associated information signaling from a scheduler. Each of the pipeline blocks respective... | 01/26/2010 |
| 7444495 | Processor and programmable logic computing arrangement A computing arrangement including a processor and programmable logic. In various embodiments, the arrangement includes an instruction processing circuit coupled to a programmable logic circuit, and a memory arrangement coupled to the instruction processing circuit a... | 10/28/2008 |
| 7426628 | Run-time node prefetch prediction in dataflow graphs A method for run-time prediction of a next caller of a shared functional unit, wherein the shared functional unit is operable to be called by two or more callers out of a plurality of callers. The shared functional unit and the plurality of callers are operable to e... | 09/16/2008 |
| 7404066 | Active memory command engine and method A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also g... | 07/22/2008 |
| 7370123 | Information processing apparatus A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A ... | 05/06/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7363472 | Memory access consolidation for SIMD processing elements having access indicators A data processing apparatus includes a SIMD (Single Instruction Multiple Data) array (10) of processing elements. The processing elements are operably divided into a plurality of processing blocks, the processing blocks being operable to process respective gr... | 04/22/2008 |
| 7360035 | Atomic read/write support in a multi-module memory configuration Efficient transfer of data to and from random access memory is described. Multiple request sources and a memory system comprise memory modules having memory banks, each bank containing rows of data. The retrieval comprises transferring all data pursuant to a given r... | 04/15/2008 |
| 7349956 | System and method for accessing and operating personal computers remotely A remote access device is disclosed for capturing, digitizing and communicating video signals from a host computer to a remote computer. The remote computer returns keyboard and mouse signals through the remote access device to the host computer to control the host ... | 03/25/2008 |
| 7336666 | Data transport for bit-interleaved streams supporting lane identification with invalid streams A method for generating a channel stream. The method generally comprises the steps of (A) transforming a plurality of data streams, wherein every data stream entering the channel stream experiences a unique transformation and (B) serializing the data streams as tran... | 02/26/2008 |
| 7324564 | Transmitting odd-sized packets over a double data rate link A method may involve: receiving an even number of odd-sized packets for transmission over a double data rate link; re-packetizing the even number of odd-sized packets into several even-sized packets; transmitting the even-sized packets over the double data rate link... | 01/29/2008 |
| 7305649 | Automatic generation of a streaming processor circuit A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of cir... | 12/04/2007 |
| 7290123 | System, device and method of maintaining in an array loop iteration data related to branch entries of a loop detector A loop detector with an array to store a counter of loop iterations, where the number of entries in the array may be, for example, smaller than the number of entries in the loop detector. Entries in the array may, for example, be associated with more than one entry ... | 10/30/2007 |
| 7287146 | Array-type computer processor An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and th... | 10/23/2007 |
| 7274705 | Method and apparatus for reducing clock speed and power consumption A system for reducing clock speed and power consumption in a network chip. The system has a core that transmits and receives signals at a first clock speed. A receive buffer is in communication with the core and configured to transmit the signals to the core at the ... | 09/25/2007 |
| 7260558 | Simultaneously searching for a plurality of patterns definable by complex expressions, and efficiently generating data for such searching An apparatus, a carrier medium carrying computer readable code to implement a method, and a method for searching for a plurality of patterns definable by complex expressions, and further, for efficiently generating data for such searching. One method includes accept... | 08/21/2007 |
| 7237216 | Clock gating approach to accommodate infrequent additional processing latencies A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal... | 06/26/2007 |
| 7227994 | Method and apparatus for imbedded pattern recognition using dual alternating pointers A method and apparatus for finding a reference pattern (RP) with K elements imbedded in an input pattern IP with repeating substrings uses dual pointers to point to elements in the RP to compare with input elements sequentially clocked from the IP. The dual pointers... | 06/05/2007 |
| 7200138 | Physical medium dependent sub-system with shared resources for multiport xDSL system A physical medium dependent (PMD) transport subsystem is disclosed which is used in an xDSL communication system. The PMD subsystem coordinates movement of data from an analog front end to a logical pipeline based TC layer, and exchanges common data objects with the... | 04/03/2007 |
| 7171401 | Data processing system and method having high availability A system such as an accounting system providing highly reliable continuous operation services at low cost. The system is configured to transfer data asynchronously between a main system that operates in daytime mode and a subsystem that operates in nighttime mode. A... | 01/30/2007 |
| 7149876 | Method and apparatus for a shift register based interconnection for a massively parallel processor array A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still allowing for use of the simple 1-bit interconnection network to transf... | 12/12/2006 |
| 7146480 | Configurable memory system A configurable memory system is disclosed, which includes a processor-to-memory network, a memory-to-processor network, and a plurality of memory modules. Both networks in turns include a plurality of transport cells that can be configured to implement various trans... | 12/05/2006 |
| 7130986 | Determining if a register is ready to exchange data with a processing element According to some embodiments, it is determined if a register is ready to exchange data with a processing element. ... | 10/31/2006 |
| 7111179 | Method and apparatus for optimizing performance and battery life of electronic devices based on system and application parameters An electronic device (e.g., computer system, etc.) employing dynamic power management of the present invention adjusts power consumption in accordance with an analysis of parameters and events occurring over one or more time-periods. Preferably, the electronic devic... | 09/19/2006 |
| 7100020 | Digital communications processor An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue m... | 08/29/2006 |
| 7085913 | Hub/router for communication between cores using cartesian coordinates A method and structure for an integrated circuit is disclosed. The invention includes a plurality of logic cores, a plurality of local hubs connected to said logic cores, and a plurality of global hubs connected to said local hubs. The local hubs and the global hubs... | 08/01/2006 |
| 7085285 | xDSL communications systems using shared/multi-function task blocks A communications system including a shared signal circuit for performing a set of signal processing operations on both receive data and transmit data. The signal processing circuit is also shared by a plurality of communication ports. To further enhance operation of... | 08/01/2006 |
| 7075941 | Scaleable architecture for multiple-port, system-on-chip ADSL communications systems A multi-port communications system is described, which includes hardware based subsystems for performing both physical medium dependent operations and transport convergence operations on a data transmission. A software based subsystem performs other operations as ne... | 07/11/2006 |
| 7062762 | Partitioning symmetric nodes efficiently in a split register file architecture The present invention provides methods specifically geared to finding natural splits in wide, nearly symmetric dependence graphs and assigning the components of the split to clusters in a VLIW processor. The basic approach of these methods is to assign a node n of t... | 06/13/2006 |
| 7032223 | Transport convergence sub-system with shared resources for multiport xDSL system A transport convergence (TC) subsystem for use as a form of logical pipeline processor is disclosed. The TC subsystem includes a number of ASIC computing blocks interconnected through a local bus for transferring data objects used as a form of common data I/O for ea... | 04/18/2006 |
| 7032061 | Multimaster bus system A multimaster bus system includes a bus for connecting to devices connected thereto and a bus controller that controls the bus and/or the bus grant. The multimaster bus system includes providing the bus with data and/or signals paths. The bus controller can alter st... | 04/18/2006 |
| 7017136 | Architecture and interconnect scheme for programmable logic circuits An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between l... | 03/21/2006 |
| 7003594 | Streaming protocol for storage devices Various embodiments of systems and methods for implementing a streaming I/O protocol are disclosed. In some embodiments, a method may involve: receiving a packet initiating a streaming write operation, where the packet indicates that the size of the streaming write ... | 02/21/2006 |
| 7000090 | Center focused single instruction multiple data (SIMD) array system A center focussed SIMD array system including an SIMD array including a plurality of processing elements arranged in a number of columns and rows and having two mutually perpendicular axes of symmetry defining four quadrants; and a sequencer circuit for moving the d... | 02/14/2006 |
| 7000022 | Flow of streaming data through multiple processing modules Frame-based streaming data flows through a graph of multiple interconnected processing modules. The modules have a set of performance parameters whose values specify the sensitivity of each module to the selection of certain resources of a system. A user specifies o... | 02/14/2006 |
| 6993639 | Processing instruction addressed by received remote instruction and generating remote instruction to respective output port for another cell Embodiments of the invention relate to a processing cell for use in computing systems. Generally, a processing cell generates remote instructions to be received and processed by at least one other processing cell. A processing cell may include a program counter, an ... | 01/31/2006 |
