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| Number | Title | Issue Date |
| 8103853 | Intelligent fabric system on a chip A chip having an intelligent fabric may include a soft application processor, a reconfigurable hardware intelligent processor, a partitioned memory storage, and an interface to an external reconfigurable communication processor. The reconfigurable hardware intellige... | 01/24/2012 |
| 7979672 | Multi-core processors for 3D array transposition by logically retrieving in-place physically transposed sub-array data A method and system for transposing a multi-dimensional array for a multi-processor system having a main memory for storing the multi-dimensional array and a local memory is provided. One implementation involves partitioning the multi-dimensional array into a number... | 07/12/2011 |
| 7930518 | Method for manipulating data in a group of processing elements to perform a reflection of the data A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that... | 04/19/2011 |
| 7913062 | Method of rotating data in a plurality of processing elements A method of rotating data in a plurality of processing elements comprises a plurality of shifting operations and a plurality of storing operations, with the shifting and storing operations coordinated to enable a three shears operation to be performed on the data. T... | 03/22/2011 |
| 7877401 | Pattern matching A method for processing data for pattern matching includes: receiving a first sequence of data values; and generating a second sequence of data values based on the first sequence and one or more patterns and history of data values in the first sequence, wherein the ... | 01/25/2011 |
| 7676648 | Method for manipulating data in a group of processing elements to perform a reflection of the data A method for generating a reflection of data in a plurality of processing elements comprises shifting the data along, for example, each row in the array until each processing element in the row has received all the data held by every other processing element in that... | 03/09/2010 |
| 7606996 | Array type operation device An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of... | 10/20/2009 |
| 7581080 | Method for manipulating data in a group of processing elements according to locally maintained counts The present invention is capable of placing or loading input data into a 2D or 3D array of processing elements interconnected in a variety of ways, and moving the data around by using a combination of shifts, e.g. north, south, east, west, which can be combined in a... | 08/25/2009 |
| 7395082 | Method and system for handling events in an application framework for a wireless device Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI wireless framework. An identity of the acquired MMI event may be deter... | 07/01/2008 |
| 7353368 | Method and apparatus for achieving architectural correctness in a multi-mode processor providing floating-point support A method comprising fetching an input from at least one of a plurality of floating-point registers and detecting whether the input includes a token. If the token is detected in the input, checking what mode the processor is in. If the processor is in a first mode, p... | 04/01/2008 |
| 7353429 | System and method using hardware buffers for processing microcode trace data Debugging microcode is facilitated by a hardware assist that takes over from the microcode the basic management of handling the data for a trace entry, thereby reducing the load on the microcode to a single micro-instruction per trace operation and thereby permittin... | 04/01/2008 |
| 7350057 | Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for executing vector instructions each defining multiple value pairs; and an ins... | 03/25/2008 |
| 7318143 | Reuseable configuration data An information processor for executing a program comprising a plurality of separate program instructions is provided. The processor comprises processing logic operable to individually execute said separate program instructions of said program, an operand store opera... | 01/08/2008 |
| 7277470 | Multi-user detection in an MC-CDMA telecommunication system A multi-user detection method and device for a receiver in a multi-carrier code division multiple access telecommunication system, each communication to or from a user of the system being coded with a signature, the signal received by said receiver being decomposed ... | 10/02/2007 |
| 7277542 | Stream cipher encryption application accelerator and methods thereof A system for encrypting and decrypting data formed of a number of bytes using the ARCFOUR encryption algorithm is disclosed. The system includes a system bus and an encryption accelerator arranged to execute the encryption algorithm coupled to the system bus. A syst... | 10/02/2007 |
| 7236982 | Computer systems and methods for platform independent presentation design Methods, computer systems and computer program products for constructing a presentation in a platform independent manner. A layout is defined that includes a top split. The top split includes a first orientation parameter specifying an orientation for any daughter s... | 06/26/2007 |
| 7237086 | Configuring a management module through a graphical user interface for use in a computer system A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the customization program to customize the baseboard management controller based ... | 06/26/2007 |
| 7219212 | Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one aspect, the processor supports three possible instruction sizes while maint... | 05/15/2007 |
| 7200287 | Method and apparatus for image processing, and a computer product The image processing apparatus is provided with a plural memory controllers, each of which controls a RAM. The memory controllers are connected to an SIMD type arithmetic processing section. A control register is connected to the memory controllers. The control regi... | 04/03/2007 |
| 7191321 | Microengine for parallel processor architecture A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control ... | 03/13/2007 |
| 7191432 | High frequency compound instruction mechanism and method for a compare operation in an arithmetic logic unit A high-frequency compound instruction mechanism and method allows performing a common compare immediate function before an add function has completed, thereby reducing the number of cycles to perform the add-compare function. By increasing the speed of performing th... | 03/13/2007 |
| 7191312 | Configurable interconnection of multiple different type functional units array including delay type for different instruction processing An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input ... | 03/13/2007 |
| 7162713 | Difference engine method and apparatus A method and apparatus for analyzing and formatting strings of data, such as data derived from software processes running on two data processors. In one embodiment, a plurality of different data strings are initialized building a symbol array, and finding difference... | 01/09/2007 |
| 7155466 | Policy-based management of a redundant array of independent nodes An archive cluster application runs in a distributed manner across a redundant array of independent nodes. Each node preferably runs a complete archive cluster application instance. A given nodes provides a data repository, which stores up to a large amount (e.g., a... | 12/26/2006 |
| 7149876 | Method and apparatus for a shift register based interconnection for a massively parallel processor array A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still allowing for use of the simple 1-bit interconnection network to transf... | 12/12/2006 |
| 7146405 | Computer node architecture comprising a dedicated middleware processor The computer node architecture provides a separate computer for the execution of the respective one of the application software and the middleware software, with an interface precisely defined in the time and value range provided between said two computers, and thus... | 12/05/2006 |
| 7103882 | Optimization apparatus, complier program, optimization method and recording medium An optimization apparatus (compiler program, method and recording medium) for changing the order of execution of instructions in a program to be optimized includes an exception occasion instruction detection section which detects a first instruction having a possibi... | 09/05/2006 |
| 7100020 | Digital communications processor An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue m... | 08/29/2006 |
| 7089159 | Method and apparatus for matrix reordering and electronic circuit simulation A matrix reordering method performs reordering of elements of a coefficient matrix created based on coefficients of linear simultaneous equations whose solutions are to be produced by parallel processing of processors of a computer in accordance with Gaussian elimin... | 08/08/2006 |
| 7089275 | Block-partitioned technique for solving a system of linear equations represented by a matrix with static and dynamic entries One embodiment of the present invention provides a system that uses a block-partitioned technique to efficiently solve a system of linear equations. The system first receives a matrix that specifies the system of linear equations to be used in performing a time-base... | 08/08/2006 |
| 7058790 | Cascaded event detection modules for generating combined events interrupt for processor action An eventpoint chaining apparatus for generalized event detection and action specification in a processing environment is described. In one aspect, the eventpoint chaining apparatus includes a first processor which has a programmable eventpoint module with an input t... | 06/06/2006 |
| 7055019 | Matched instruction set processor systems and method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms This invention relates to matched instruction set processor systems and a method, system, and apparatus to efficiently design and implement matched instruction set processor systems by mapping system designs to re-configurable hardware platforms. The method includes... | 05/30/2006 |
| 7035991 | Surface computer and computing method using the same A surface computer includes an address generator for generating an address for adjusting surface region data concerning at least a storage region and a concurrent computer, provided at a subsequent stage of the address generator, having a plurality of unit computers... | 04/25/2006 |
| 7000093 | Cellular automaton processing microprocessor prefetching data in neighborhood buffer A cellular automaton cache memory architecture. On a micro-processor that is also capable of executing general-purpose instructions, a cache memory is provided to store instructions and data for use by the processor. The cache memory is further capable of storing da... | 02/14/2006 |
| 6967950 | Pull transfers and transfer receipt confirmation in a datapipe routing bridge In a network of digital signal processor nodes connected in a peer-to-peer relationship, a data packet sent to a node causes a return transmission from that node. The requester digital signal processor sends a data packet to a target digital signal processor. Upon a... | 11/22/2005 |
| 6944607 | Aggregated clustering method and system An aggregated data clustering method and system. First, the data points to be clustered and a size parameter are received. The size parameter specifies the number of data points to be moved at one time in the clustering algorithm. Next, the data points are clustered... | 09/13/2005 |
| 6922716 | Method and apparatus for vector processing A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and second vector arithmetic logic unit wherein the first register file has a... | 07/26/2005 |
| 6915410 | Compiler synchronized multi-processor programmable logic device with direct transfer of computation results among processors A system for designing and implementing digital integrated circuits utilizing a set of synchronized sequencers that permit quick and efficient parallel processing of system level designs. The system and method converts digital schematics and hardware description lan... | 07/05/2005 |
| 6907513 | Matrix processing method of shared-memory scalar parallel-processing computer and recording medium In accordance with a parallel matrix processing method adopted in a shared-memory scalar computer, a matrix to be subjected to LU factorization is divided into a block D of the diagonal portion and blocks beneath the D diagonal block such as L1, L2 and... | 06/14/2005 |
| 6836839 | Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The ... | 12/28/2004 |
