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| Number | Title | Issue Date |
| 8185719 | Message routing scheme for an array having a switch with address comparing component and message routing component Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to ... | 05/22/2012 |
| 8161267 | Methods and apparatus for scalable array processor interrupt detection and response Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable ... | 04/17/2012 |
| 8151090 | Sequentially propagating instructions of thread through serially coupled PEs for concurrent processing respective thread on different data and synchronizing upon branch A systolic data processing apparatus includes a processing element (PE) array and control unit. The PE array comprises a plurality of PEs, each PE executing a thread with respect to different data according to an input instruction and pipelining the instruction at e... | 04/03/2012 |
| 8151089 | Array-type processor having plural processor elements controlled by a state control unit A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of... | 04/03/2012 |
| 8086824 | Stream processing system having a reconfigurable memory module A stream processing system includes a stream processing module coupled to a memory module and operable so as to fetch stream elements from the memory module, to process the stream elements fetched thereby, and to store processed stream elements in the memory module.... | 12/27/2011 |
| 8078835 | Reconfigurable array processor for floating-point operations A processor for performing floating-point operations includes an array of processing elements arranged to enable a floating-point operation. Each processing element includes an arithmetic logic unit to receive two input values and perform integer arithmetic on the r... | 12/13/2011 |
| 8078834 | Processor architectures for enhanced computational capability A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each of the issued instructions executes in successive compute engines of a... | 12/13/2011 |
| 8028150 | Runtime instruction decoding modification in a multi-processing array A method and system for decoding and modifying processor instructions in runtime according to certain rules in order to separately control processing elements embedded within a multi-processor array using a single instruction. The present invention allows multiple p... | 09/27/2011 |
| 7987340 | Communications in a processor array Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving ... | 07/26/2011 |
| 7966475 | Parallel data processing apparatus A data processor comprises a plurality of processing elements arranged for parallel processing of data, and a controller for controlling the plurality of processing elements. The controller is operable to determine respective status information for a plurality of pr... | 06/21/2011 |
| 7962717 | Message routing scheme Each possessor node in an array of nodes has a respective local node address, and each local node address comprises a plurality of components having an order of addressing significance from most to least significant. Each node comprises: mapping means configured to ... | 06/14/2011 |
| 7958332 | Parallel data processing apparatus A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit ope... | 06/07/2011 |
| 7934075 | Method and apparatus for monitoring inputs to an asyncrhonous, homogenous, reconfigurable computer array A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously and operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another ... | 04/26/2011 |
| 7904695 | Asynchronous power saving computer A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12)... | 03/08/2011 |
| 7882333 | Architectural enhancements to CPU microcode load mechanism using inter processor interrupt messages A method for loading microcode to a plurality of cores within a processor. The method includes loading the microcode to a first core of the plurality of cores within the processor system and generating a broadcast inter process interrupt (IPI) message via the first ... | 02/01/2011 |
| 7870365 | Matrix of processors with data stream instruction execution pipeline coupled to data switch linking to neighbor units by non-contentious command channel / data channel In some embodiments, control and data messages are transmitted non-contentiously over corresponding control and data channels of inter-processor links in a matrix of mesh-interconnected matrix processors. A data stream instruction executed by a user thread of an ins... | 01/11/2011 |
| 7840778 | Processor cluster architecture and associated parallel processing methods A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors as... | 11/23/2010 |
| 7840779 | Line-plane broadcasting in a data communications network of a parallel computer Methods, apparatus, and products are disclosed for line-plane broadcasting in a data communications network of a parallel computer, the parallel computer comprising a plurality of compute nodes connected together through the network, the network optimized for point ... | 11/23/2010 |
| 7827385 | Effecting a broadcast with an allreduce operation on a parallel computer A parallel computer comprises a plurality of compute nodes organized into at least one operational group for collective parallel operations. Each compute node is assigned a unique rank and is coupled for data communications through a global combining network. One co... | 11/02/2010 |
| 7769981 | Row of floating point accumulators coupled to respective PEs in uppermost row of PE array for performing addition operation Provided is a parallel processor for supporting a floating-point operation. The parallel processor has a flexible structure for easy development of a parallel algorithm involving multimedia computing, requires low hardware cost, and consumes low power. To support fl... | 08/03/2010 |
| 7752421 | Parallel-prefix broadcast for a parallel-prefix operation on a parallel computer A parallel-prefix broadcast for a parallel-prefix operation on a parallel computer includes: configuring, on each node, a parallel-prefix contribution buffer for storing the node's parallel-prefix contribution; configuring, on each node, a parallel-prefix results bu... | 07/06/2010 |
| 7650484 | Array—type computer processor with reduced instruction storage An array-type computer processor including a data path unit communicating with a state control unit obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained in... | 01/19/2010 |
| 7603541 | Array synchronization with counters A method is disclosed for achieving synchronization in an array of semi-synchronous devices. A processor array has an array of processor elements, wherein each of said processor elements comprises a cycle counter, and a master processor element is able to transmit c... | 10/13/2009 |
| 7596678 | Method of shifting data along diagonals in a group of processing elements to transpose the data A transpose of data appearing in a plurality of processing elements comprises shifting the data along diagonals of the plurality of processing elements until the processing elements in the diagonal have received the data held by every other processing element in tha... | 09/29/2009 |
| 7577821 | IC containing matrices of plural type operation units with configurable routing wiring group and plural delay operation units bridging two wiring groups An integrated circuit device comprising a data processing block including a first matrix and a second matrix is disclosed. The first matrix and the second matrix respectively include a plurality of types of operation units and a wiring group for connecting the plura... | 08/18/2009 |
| 7574582 | Processor array including delay elements associated with primary bus nodes There is disclosed a processor array, which achieves an approximately constant latency. Communications to and from the farthest array elements are suitably pipelined for the distance, while communications to and from closer array elements are deliberately “over-pi... | 08/11/2009 |
| 7574581 | Cross-chip communication mechanism in distributed node topology to access free-running scan registers in clock-controlled components A method of communicating between processing units on different integrated circuit chips in a multi-processor computer system by issuing a command from a source processing unit to a destination processing unit, receiving the command at the destination processing uni... | 08/11/2009 |
| 7506134 | Hardware resource based mapping of cooperative thread arrays (CTA) to result matrix tiles for efficient matrix multiplication in computing system comprising plurality of multiprocessors The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs t... | 03/17/2009 |
| 7480785 | Parallel processing device and parallel processing method A row decoding circuit (171) outputs a select signal to a row set in a row range setting unit (172) to select a select signal line (103), processing results from processing circuits (102) on this row are output to a data output line (1... | 01/20/2009 |
| 7457939 | Processing system with dedicated local memories and busy identification A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a contro... | 11/25/2008 |
| 7451293 | Array of Boolean logic controlled processing elements with concurrent I/O processing and instruction sequencing A computer processor having an integrated instruction sequencer, array of processing engines, and I/O controller. The instruction sequencer sequences instructions from a host, and transfers these instructions to the processing engines, thus directing their operation... | 11/11/2008 |
| 7441100 | Processor synchronization in a multi-processor computer system A method for synchronizing a plurality of processors of a multi-processor computer system on a synchronization point is disclosed. The method includes triggering a first set of processors, using a lead processor of the plurality of processors when the lead processor... | 10/21/2008 |
| 7426448 | Method and apparatus for diagnosing broken scan chain based on leakage light emission A mechanism for diagnosing broken scan chains based on leakage light emission is provided. An image capture mechanism detects light emission from leakage current in complementary metal oxide semiconductor (CMOS) devices. The diagnosis mechanism identifies devices wi... | 09/16/2008 |
| 7418541 | Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor A method and apparatus are provided for a support interface for memory-mapped resources. A support processor sends a sequence of commands over and FSI interface to a memory-mapped support interface on a processor chip. The memory-mapped support interface updates mem... | 08/26/2008 |
| 7401333 | Array of parallel programmable processing engines and deterministic method of operating the same The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least some threads communicate with each other through communication objects e... | 07/15/2008 |
| 7392350 | Method to operate cache-inhibited memory mapped commands to access registers In a multiprocessor environment, by executing cache-inhibited reads or writes to registers, a scan communication is used to rapidly access registers inside and outside a chip originating the command. Cumbersome locking of the memory location may be thus avoided. Set... | 06/24/2008 |
| 7373440 | Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format A switch/network adapter port (“SNAP”) for clustered computers employing multi-adaptive processor (“MAP™”, a trademark of SRC Computers, Inc.) elements in a dual in-line memory module (“DIMM”) or Rambus™ in-line memory module (“RIMM”) format to s... | 05/13/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
| 7370116 | Approach to minimize worst-case queuing delay for a switching communication system with transmission constraints An approach for minimizing queuing delay of packets is disclosed. M number of queues are configured to store packets. A memory stores a search order table that has table entries corresponding to the M queues. Specifically, the table entries store values that corresp... | 05/06/2008 |
| 7369683 | Imaging device In an imaging device of the present invention, an imaging element 2 is driven in a thinning read-out mode for reading out signal charges from a subset of pixels, or in an all-pixels read-out mode for reading out signal charges from all pixels. When the imagin... | 05/06/2008 |
