Bizarre Patents
Crispy Chip Sandwich and Process of Producing a Sandwich Product
A food product comprising a multilayer cookie or snack having outer layers formed from a crispy type edible food product such as a potato chip or corn chip, etc. with an intermediate marshmallow layer being in contact with the inner surface of each crispy chip and one or more filler substances.
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| Number | Title | Issue Date |
| 8112612 | Processing system with interspersed processors using selective data transfer through communication elements A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of pro... | 02/07/2012 |
| 8082418 | Method and apparatus for coherent device initialization and access A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-proc... | 12/20/2011 |
| 8078833 | Microprocessor with highly configurable pipeline and executional unit internal hierarchal structures, optimizable for different types of computational functions The invention resides in a flexible data pipeline structure for accommodating software computational instructions for varying application programs and having a programmable embedded processor with internal pipeline stages the order and length of which varies as fast... | 12/13/2011 |
| 8069333 | Converting logical to real number to access shared configuration information in event driven state transiting reconfigurable system A data processing device comprises a state manager for determining a logic number of configurational information to be used in a next state, the logic number representing information on a mutual relationship between items of configurational information included in a... | 11/29/2011 |
| 8055880 | Reconfigurable circuit having a pipeline structure for carrying out time division multiple processing The reconfigurable circuit of the present invention in which time division multiple processing is possible has a pipeline structure with the number of stages of an integral multiple of a given number, and comprises a plurality of processor elements having a processi... | 11/08/2011 |
| 8046564 | Reconfigurable paired processing element array configured with context generated each cycle by FSM controller for multi-cycle floating point operation Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources inclu... | 10/25/2011 |
| 8024548 | Integrated circuit microprocessor that constructs, at run time, integrated reconfigurable logic into persistent finite state machines from pre-compiled machine code instruction sequences A processor, integrated with re-configurable logic and memory elements, is disclosed which is to be used as part of a shared memory, multiprocessor computer system. The invention utilizes the re-configurable elements to construct persistent finite state machines bas... | 09/20/2011 |
| 8006067 | Flexible results pipeline for processing element A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each other, to processing logic of the processing element and to a neighborhood connection register configured to ... | 08/23/2011 |
| 7873811 | Polymorphous computing fabric Fabric-based computing systems and methods are disclosed. A fabric-based computing system can include a polymorphous computing fabric that can be customized on a per application basis and a host processor in communication with said polymorphous computing fabric. The... | 01/18/2011 |
| 7870364 | Reconfigurable apparatus and method for providing multiple modes A reconfigurable processor (RP) structure is provided, and particularly, a multi-mode providing apparatus including an exclusive coarse-grained array unit for each mode and a multi-mode providing method thereof are provided. The multi-mode providing apparatus includ... | 01/11/2011 |
| 7849288 | Alternately selecting memory units to store and retrieve configuration information in respective areas for a plurality of processing elements to perform pipelined processes A reconfigurable circuit and control method therefor, capable of enhancing efficiency of implementation of a pipeline process in processing elements and improve processing performance. Processing elements are reconfigured to form a circuit based on configuration inf... | 12/07/2010 |
| 7840777 | Method and apparatus for directing a computational array to execute a plurality of successive computational array instructions at runtime A general purpose computing system comprises a novel apparatus and method for data processing. The computing system design of one application of the present invention includes an instruction pipe having a decompression circuit, a reprogrammable logic unit and a data... | 11/23/2010 |
| 7809926 | Systems and methods for reconfiguring on-chip multiprocessors A reconfigurable multiprocessor system including a number of processing units and components enabling executing sequential code collectively at processing units and enabling changing the architectural configuration of the processing units. ... | 10/05/2010 |
| 7774580 | Array processor having reconfigurable data transfer capabilities A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for con... | 08/10/2010 |
| 7765382 | Propagating reconfiguration command over asynchronous self-synchronous global and inter-cluster local buses coupling wrappers of clusters of processing module matrix A semiconductor device includes a plurality of processing clusters that operate synchronously internally and arranged in a M×N matrix. Each processing cluster is formed as a plurality of processing elements and clocked buses that interconnect the processing element... | 07/27/2010 |
| 7752419 | Method and system for managing hardware resources to implement system functions using an adaptive computing architecture The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The ... | 07/06/2010 |
| 7752420 | Configuration layout number controlled adjustable delaying of connection path changes among processors in array to reduce transition glitches Occurrence and propagation of glitches caused by changing the path layout are suppressed, thereby reducing the power consumption. An array-type processor comprises a plurality of processor elements and can change the path layout relating to data transmission/recepti... | 07/06/2010 |
| 7739481 | Parallelism with variable partitioning and threading A programmable device includes multiple function unit control memories connected to multiple sequencers through an address selection network. Sequencers are dynamically assigned to function unit control memories allowing intermediate level including statement level ... | 06/15/2010 |
| 7734896 | Enhanced processor element structure in a reconfigurable integrated circuit device A reconfigurable integrated circuit device which converts an arbitrary calculation state dynamically, based on configuration data, includes a plurality of processor elements, each of which has an input terminal, an output terminal, a plurality of arithmetic units wh... | 06/08/2010 |
| RE41293 | Multiprocessor computer having configurable hardware system domains Global address and data routers interconnect individual system units each having its own processors, memory, and I/O. A domain filter coupled to the routers dynamically defines groups of system units as domains and clusters of domains which have both software and ha... | 04/27/2010 |
| 7702884 | Semiconductor integrated circuit with selected signal line coupling A semiconductor integrated circuit includes a reconfigurable circuit including a plurality of computing units interconnected in a reconfigurable manner, a processing circuit including at least one of a fixed logic circuit configured to perform predetermined processi... | 04/20/2010 |
| 7669035 | Systems and methods for reconfigurable computing A processing system includes a communication bus. a controller, an Input/Output (“I/O”) block, and reconfigurable logic segments (e.g., reconfigurable units). Individually reconfigurable logic segments are part of a single chip. A communication bus is in electri... | 02/23/2010 |
| 7627737 | Processing element and method connecting registers to processing logic in a plurality of configurations A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each other, to processing logic of the processing element and to a neighborhood connection register configured to ... | 12/01/2009 |
| 7613899 | Reconfigurable data processing device and method A reconfigurable data processing device equipped with a plurality of data processing units controls timing of switching contents of data processing executed by each of the plurality of data processing units for each of a plurality of data processing operations. ... | 11/03/2009 |
| 7603540 | Using field programmable gate array (FPGA) technology with a microprocessor for reconfigurable, instruction level hardware acceleration A method for dynamically programming Field Programmable Gate Arrays (FPGAs) in a coprocessor, the coprocessor coupled to a processor, includes: beginning an execution of an application by the processor; receiving an instruction from the processor to the coprocessor ... | 10/13/2009 |
| 7568084 | Semiconductor integrated circuit including multiple basic cells formed in arrays A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in c... | 07/28/2009 |
| 7509479 | Reconfigurable global cellular automaton with RAM blocks coupled to input and output feedback crossbar switches receiving clock counter value from sequence control unit The invention relates to a computer containing a RAM-based primary part (Ht) with a stucturable RAM unit (2). On the input side, a first crossbar switch (1) is located upstream of said unit and a second crossbar switch (3) is located downstream.... | 03/24/2009 |
| 7464251 | Method and apparatus for configuring arbitrary sized data paths comprising multiple context processing elements A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most signifi... | 12/09/2008 |
| 7418575 | Long instruction word processing with instruction extensions A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of computational instructions and long instruction word instructions with ... | 08/26/2008 |
| 7418574 | Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively,... | 08/26/2008 |
| 7418579 | Component with a dynamically reconfigurable architecture The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through interconnections so as to enable processing in pipeline or parallel mode ... | 08/26/2008 |
| 7415594 | Processing system with interspersed stall propagating processors and communication elements A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of pro... | 08/19/2008 |
| 7408382 | Configurable circuits, IC's, and systems Some embodiments of the invention provide a first configurable integrated circuit (IC) that has a first configurable IC design. The first configurable IC implements a second IC design that is specified for a second IC that is to operate a particular design rate. The... | 08/05/2008 |
| 7398380 | Dynamic hardware partitioning of symmetric multiprocessing systems Dynamic hardware partitioning of symmetric multiprocessing systems enables on-the-fly provisioning of servers of varying performance characteristics by configuring physical partitions having selectable numbers of processors. Processors are directed to disable includ... | 07/08/2008 |
| 7386704 | Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of pipeline units in the pipeline accelerator, one can increase the accel... | 06/10/2008 |
| 7383424 | Computer architecture containing processor and decoupled coprocessor A computer system comprises a first processor 1 and a second processor 2 for use as a coprocessor to the first processor 1. The system has a main memory 3. The system also has a decoupling element 8 such that instructions are passe... | 06/03/2008 |
| 7380100 | Data processing system and control method utilizing a plurality of date transfer means The present invention provides a data processing system that includes a plurality of processing units and first, second, and third data transfer means. The first data transfer means connects a plurality of processing units in a network, exchanges first data, and con... | 05/27/2008 |
| 7379418 | Method for ensuring system serialization (quiesce) in a multi-processor environment A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one processor changes the system state. Architected designs where latencies ... | 05/27/2008 |
| 7376811 | Method and apparatus for performing computations and operations on data using data steering A data processing system architecture is based upon a hardware engine that includes a plurality of functional units and data routing units that interconnect the functional units. The hardware engine performs operations and computations on data as the data traverses ... | 05/20/2008 |
| 7373111 | Communication access apparatus, systems, and methods An apparatus and a system, as well as a method and article, may operate to reserve access for a source device included in a plurality N of source devices to N−1 logical channels accessible by a set of target devices included in the plurality of source devices by c... | 05/13/2008 |
