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"What, sir, would you make a ship sail against the wind and currents by lighting a bonfire under her deck? I pray you, excuse me, I have not the time to listen to such nonsense."
Napoleon Bonaparte ; When told of the Robert Fulton steamboat
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| Number | Title | Issue Date |
| 7895412 | Programmable arrayed processing engine architecture for a network switch A programmable processing engine processes transient data within an intermediate network station of a computer network. The engine comprises an array of processing elements symmetrically arrayed as rows and columns, and embedded between input and output buffer units... | 02/22/2011 |
| 7664928 | Method and apparatus for providing user-defined interfaces for a configurable processor A technique that improves both processor performance and associated data bandwidth through user-defined interfaces that can be added to a configurable and extensible microprocessor core. These interfaces can be used to communicate status or control information and t... | 02/16/2010 |
| 7519793 | Facilitating inter-DSP data communications A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core couple... | 04/14/2009 |
| 7493468 | Method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing A method for broadcasting instructions/data to a plurality of processors in a multiprocessor device via aliasing is provided. In order to broadcast data to a plurality of processors, a control processor writes to the registers that store the identifiers of the proce... | 02/17/2009 |
| 7451292 | Methods for transmitting data across quantum interfaces and quantum gates using same Quantum gaps exist between an origin and a destination that heretofore have prevented reliably utilizing the advantages of quantum computing. To predict the outcome of instructions with precision, the input data, preferably a qubit, is collapsed to a point value wit... | 11/11/2008 |
| 7428629 | Memory request / grant daemons in virtual nodes for moving subdivided local memory space from VN to VN in nodes of a massively parallel computer system A memory management mechanism a nodal having multiple processors in a massively parallel computer system dynamically configures nodal memory on demand. A respective variable-sized subdivision of nodal memory is associated with each processor in the node. A processor... | 09/23/2008 |
| 7409529 | Method and apparatus for a shift register based interconnection for a massively parallel processor array A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still allowing for use of the simple 1-bit interconnection network to transf... | 08/05/2008 |
| 7409528 | Digital signal processing architecture with a wide memory bandwidth and a memory mapping method thereof A DSP (Digital Signal Processing) architecture with a wide memory bandwidth and a memory mapping method thereof. The DSP architecture includes: a first communication port; first, second, and third memory devices, which are connected with the first communication port... | 08/05/2008 |
| 7404066 | Active memory command engine and method A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also g... | 07/22/2008 |
| 7398368 | Atomic operation involving processors with different memory transfer operation sizes Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that operate on different sized register lines. A main memory address conta... | 07/08/2008 |
| 7386689 | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circui... | 06/10/2008 |
| 7369683 | Imaging device In an imaging device of the present invention, an imaging element 2 is driven in a thinning read-out mode for reading out signal charges from a subset of pixels, or in an all-pixels read-out mode for reading out signal charges from all pixels. When the imagin... | 05/06/2008 |
| 7370046 | Sort processing method and sort processing apparatus Disclosed are a sort processing method and a sort processing apparatus, which, in a computer or data processing, compare magnitudes of pieces of data input by hardware, rearrange the pieces of data in accordance with a predetermined order and output the rearranged p... | 05/06/2008 |
| 7366352 | Method and apparatus for performing fast closest match in pattern recognition A method and apparatus for determining a closest match of N input patterns relative to R reference patterns using K processing units. Each of a set of input patterns are loaded into the K processing units. One of the Reference patterns is sequentially loaded into ea... | 04/29/2008 |
| 7363304 | Method and system for providing a hardware sort for a large number of items A method and system for sorting a number of items in a computer system. The sort is based on a plurality of values of a key. Each item has a value of the plurality of values. The method and system include providing plurality of stages, providing at least one switch ... | 04/22/2008 |
| 7325122 | Facilitating inter-DSP data communications A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core couple... | 01/29/2008 |
| 7305676 | Communication device configured for real time processing of user data to be transmitted A communication device is provided which has a programmable multichannel signal processor for real time processing of user data, which are to be transmitted, within the framework of a plurality of real time applications. The real time applications are each assigned ... | 12/04/2007 |
| 7305524 | Snoop filter directory mechanism in coherency shared memory system Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the... | 12/04/2007 |
| 7302548 | System and method for communicating in a multi-processor environment A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the o... | 11/27/2007 |
| 7280112 | Arithmetic logic unit temporary registers An arithmetic logic unit (ALU) in a graphics processor is described. The ALU includes circuitry for performing an operation using a first set of pixel data. The first set of pixel data is resident in a pipeline register coupled to the circuitry. A temporary register... | 10/09/2007 |
| 7275145 | Processing element with next and previous neighbor registers for direct data transfer According to some embodiments, a processing element includes (i) a next neighbor register to receive information directly from a previous processing element in a series of processing elements, and (ii) a previous neighbor register to receive information directly fro... | 09/25/2007 |
| 7272691 | Interconnect switch assembly with input and output ports switch coupling to processor or memory pair and to neighbor ports coupling to adjacent pairs switch assemblies A data processor apparatus comprises a plurality of processor elements, a memory having a plurality of parts, and a first switching element associated with the first processor element for switchably coupling the first processor element to its associated memory part ... | 09/18/2007 |
| 7268788 | Associative processing for three-dimensional graphics Associative processing methods and apparatus are described for processing graphics data for three-dimensional graphic displays, e.g., in three-dimensional games. A texture, which comprises a bitmap image used to apply a design onto the surface of a 3D computer model... | 09/11/2007 |
| 7240347 | Systems and methods for preserving the order of data A device includes an input processing unit and an output processing unit. The input processing unit dispatches first data to one of a group of processing engines, records an identity of the one processing engine in a location in a first memory, reserves one or more ... | 07/03/2007 |
| 7237087 | Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configura... | 06/26/2007 |
| 7236385 | Memory architecture A DDR SDRAM where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays. The unidirectional row logic is located in the outward periphery of its associated array, b... | 06/26/2007 |
| 7237041 | Systems and methods for automatic assignment of identification codes to devices A system and method for automatically and uniquely assigning identification codes to a plurality of slave processors. A master processor having communication port is linked to a first slave processor, which, itself, has first and second communication ports. The firs... | 06/26/2007 |
| 7222313 | Creating description files used to configure components in a distributed system The present invention provides for creating description files used to configure components in a distributed system. A computer or program developer accesses an application type. The computer or program developer accesses a hardware specification. The computer or pro... | 05/22/2007 |
| 7216215 | Data access method applicable to various platforms A data access method uses variable mask data and shift amount to write data into or read data from a data storage zone. The mask data and shift amount are determined according to starting and end data bit addresses in a bit range of the data to be read or written. T... | 05/08/2007 |
| 7210139 | Processor cluster architecture and associated parallel processing methods A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors as... | 04/24/2007 |
| 7181593 | Active memory command engine and method A command engine for an active memory receives high level tasks from a host and generates corresponding sets of either DCU commands to a DRAM control unit or ACU commands to a processing array control unit. The DCU commands include memory addresses, which are also g... | 02/20/2007 |
| 7174442 | Data addressing A method of carrying out a data fetch operation for a data-parallel processor such as a SIMD processor is described. The operation is specifically involving the use of a plurality of non-sequential data addresses. The method comprises constructing a linear address v... | 02/06/2007 |
| 7162573 | Communication registers for processing elements Various embodiments of the invention relate to communicating data between a number of processing elements (PEs) of a signal processor, using a plurality of communication registers (CCRs). For instance, a plurality of the CCRs can be shared by and mapped to the addre... | 01/09/2007 |
| 7159100 | Method for providing extended precision in SIMD vector arithmetic operations The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector regis... | 01/02/2007 |
| 7159059 | Ultra-modular processor in lattice topology A Modular Operating Topology Element (MOTE), within a software-latticed network, implements ultra-concurrent operation of a plurality of such MOTEs, as single miniaturized packages, e.g., Compact Flash, each with a full function processor (CPU), a unique resident op... | 01/02/2007 |
| 7152095 | Method and apparatus for erasing data after tampering An approach for storing and maintaining data is disclosed. One or more sensors are provided for detecting unauthorized access to a first non-volatile storage. If unauthorized access to the first non-volatile storage is detected, then the data on the first non-volati... | 12/19/2006 |
| 7149876 | Method and apparatus for a shift register based interconnection for a massively parallel processor array A system and method for using wider data paths within Processing Elements (PEs) of a Massively Parallel Array (MPP) to speed the computational performance of the PEs and the MPP array while still allowing for use of the simple 1-bit interconnection network to transf... | 12/12/2006 |
| 7146486 | SIMD processor with scalar arithmetic logic units A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different data item, where each different time interval is one of a plurality ... | 12/05/2006 |
| 7133998 | Active memory processing array topography and method An integrated active memory device includes an array of processing elements coupled to a dynamic random access memory device and to a component supplying instructions to the processing elements. The processing elements are logically arranged in a plurality of logica... | 11/07/2006 |
| 7100020 | Digital communications processor An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue m... | 08/29/2006 |
