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Vehicular Impact Signaling Device
An apparatus for the deployment of a visible plume to alert other motorists that a proximate motor vehicle has been involved in a collision.
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| Number | Title | Issue Date |
| 8122226 | Method and apparatus for dynamic partial reconfiguration on an array of processors A method and apparatus for dynamic partial reconfiguration on an array of processors. The method includes the steps of verifying if a processor is ready for dynamic partial reconfiguration to begin, deciding the degree of dynamic partial reconfiguration, including t... | 02/21/2012 |
| 8112611 | Allocating resources to partitions in a partitionable computer Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the ... | 02/07/2012 |
| 8078832 | Virtual architectures in a parallel processing environment An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing... | 12/13/2011 |
| 8046563 | Virtual architectures in a parallel processing environment An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing... | 10/25/2011 |
| 7734895 | Configuring sets of processor cores for processing instructions An integrated circuit includes a plurality of processor core. Processing instructions in the integrated circuit includes: managing a plurality of sets of processor cores, each set including one or more processor cores assigned to a function associated with executing... | 06/08/2010 |
| 7631165 | Processor organized in clusters of processing elements and cluster interconnections by a clustering process An array processor includes processing elements (00, 01, 02, 03, 10, 11, 12, 13, 20, 21, 23, 30, 31, 32, 33) arranged in clusters (e.g., 44, 46, 48, 50) to form a rectangular array (40). Inter-cluster communication paths (88) are mutually... | 12/08/2009 |
| 7606995 | Allocating resources to partitions in a partitionable computer Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the ... | 10/20/2009 |
| 7428628 | Method and apparatus for management of control flow in a SIMD device A single instruction multiple data processing device includes a plurality of processing elements. Each processing element includes an execute mask count register storing a plurality of bits. The writing updated data to registers in each processing element is enabled... | 09/23/2008 |
| 7406583 | Autonomic computing utilizing a sequestered processing resource on a host CPU An autonomic computing environment is provided by sequestering one of a plurality of processor resources, partitioning a memory, and hiding an input/output (I/O) device. One processor resource is sequestered such that the sequestered processor resource is not expose... | 07/29/2008 |
| 7401203 | Method for wiring allocation and switch configuration in a multiprocessor environment A method for wiring allocation and switch configuration in a multiprocessor computer, the method including employing depth-first tree traversal to determine a plurality of paths among a plurality of processing elements allocated to a job along a plurality of switche... | 07/15/2008 |
| 7398380 | Dynamic hardware partitioning of symmetric multiprocessing systems Dynamic hardware partitioning of symmetric multiprocessing systems enables on-the-fly provisioning of servers of varying performance characteristics by configuring physical partitions having selectable numbers of processors. Processors are directed to disable includ... | 07/08/2008 |
| 7380001 | Fault containment and error handling in a partitioned system with shared resources A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occu... | 05/27/2008 |
| 7369535 | Voice over Internet Protocol real time protocol routing A method for call signaling and media flow in a network including receiving call signaling information from an originating Voice over Internet Protocol (VoIP) endpoint, relaying the call signaling information to a destination VoIP endpoint, directing the originating... | 05/06/2008 |
| 7370159 | Microprocessor having an extended addressable space A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space. The addressable memory space is for a lower memory area and an extende... | 05/06/2008 |
| 7359959 | Method and apparatus for using a USB cable as a cluster quorum device A method for obtaining a quorum vote by a first node using a Universal Serial Bus (USB) quorum cable, wherein the USB quorum cable comprises a first end connected to a first node and a second end connected to a second node, including determining whether the USB quor... | 04/15/2008 |
| 7356701 | Data repository and method for promoting network storage of data In general, the invention features methods by which more than one client program connected to a network stores the same data item on a storage device of a data repository connected to the network. In one aspect, the method comprises encrypting the data item using a ... | 04/08/2008 |
| 7350036 | Technique to perform concurrent updates to a shared data structure A technique to perform concurrent updates to a shared data structure. At least one embodiment of the invention concurrently stores copies of a data structure within a plurality of local caches, updates the local caches with a partial result of a computation distribu... | 03/25/2008 |
| 7350131 | Error protecting groups of data words Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for use in protecting groups of data words. One embodiment manipulates these data words to generate a resultant data word and an error correction code thereon fo... | 03/25/2008 |
| 7343521 | Method and apparatus to preserve trace data A method, apparatus, and computer instructions for processing trace data in a logical partitioned data processing system. A partition causing an exception is identified in response to detecting the exception. The partition is one within a set of partitions in the lo... | 03/11/2008 |
| 7336657 | Inter-nodal data transfer system and data transfer apparatus A plurality of inter-nodal control means are provided at a connection part between an inter-nodal crossbar switch for an inter-nodal data transfer and each node so as to process one inter-nodal transfer command, and an inter-nodal transfer capacity can be variably s... | 02/26/2008 |
| 7328270 | Communication protocol processor having multiple microprocessor cores connected in series and dynamically reprogrammed during operation via instructions transmitted along the same data paths used to convey communication data A communication protocol processor is presented including a transmit unit and a receive unit, each having multiple microprocessor cores connected in series. Each microprocessor core performs an operation upon a stream of communication data, conducted along a data pa... | 02/05/2008 |
| 7315895 | Fault containment and error handling in a partitioned system with shared resources A system and method for fault containment and error handling within a domain in a partitioned computer system includes a system manager having read and write access to a resource definition table. The system manager is adapted to quiesce the system when failure occu... | 01/01/2008 |
| 7313723 | Self-reparable semiconductor and method thereof A self-reparable semiconductor comprises first and second physical layer devices each including first and second subfunctional units that cooperate to provide first and second ports associated with a multi-bit Gigabit physical layer device. A first spare physical la... | 12/25/2007 |
| 7287146 | Array-type computer processor An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and th... | 10/23/2007 |
| 7281249 | Computer forming logical partitions A computer controls I/O allocation for partitions independently of CPU allocation and, in each I/O adapter and partition, the computer has a scheduling means controlling allocation for partitions of the I/O adapter by time sharing, a means to allocate the I/O adapte... | 10/09/2007 |
| 7279930 | Architecture for routing resources in a field programmable gate array A turning structure for routing channels in a field programmable gate array, comprising a first plurality of routing channels having a first direction and a second plurality of routing channels having a second direction. The first plurality of routing channels inter... | 10/09/2007 |
| 7281055 | Routing mechanisms in systems having multiple multi-processor clusters A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exce... | 10/09/2007 |
| 7272664 | Cross partition sharing of state information A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for t... | 09/18/2007 |
| 7260673 | Method and apparatus for verifying the integrity of a content-addressable memory result Methods and apparatus are disclosed for verifying the integrity of an index or result produced by a content-addressable or associated memory or other device. A pre-computed data protection field is stored, either as part of a returned index of a content-addressable ... | 08/21/2007 |
| 7257515 | Sliding window for alert generation A method for generating alerts from a periodically sampled system is disclosed. The method includes maintaining a sampling window having a predefined number of most-recently collected samples. The method further includes calculating an alert value, the alert value r... | 08/14/2007 |
| 7257672 | Error protection for lookup operations performed on ternary content-addressable memory entries Lookup operations are performed on ternary content-addressable memory (TCAM) entries, with error protection provided. Groups of TCAM entries are programmed such that each of its entries differ by more than a predetermined calculated count of ones distance of k bits,... | 08/14/2007 |
| 7251698 | Address space management in systems having multiple multi-processor clusters A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exce... | 07/31/2007 |
| 7249351 | System and method for preparing software for execution in a dynamically configurable hardware environment A system and method for creating run time executables in a configurable processing element array is disclosed. This system and method includes the step of partitioning a processing element array into a number of defined sets of hardware accelerators, which in one em... | 07/24/2007 |
| 7246056 | Runtime parameter mapping for system simulation An electronic device and method are provided to enable simulation of a system while minimizing a requirement to reanalyze or recompile topology information during subsequent simulations of the system. Instructions representative of compiling a topology of the system... | 07/17/2007 |
| 7246217 | Interconnection arrangement of routers of processor boards in array of cabinets supporting secure physical partition A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure includes routers in service or compute proces... | 07/17/2007 |
| 7243292 | Error correction using finite fields of odd characteristics on binary hardware Binary data representing a code word of an error-correcting code is used for calculating a syndrome, wherein a given portion of the binary data comprises k groups of data bits and represents a field element of the finite field GF(pk), p being an odd prime... | 07/10/2007 |
| 7240116 | Dynamic RDF groups Described are techniques used in dynamically modifying RDF groups. A system call is issued by a host computer system to execute a remote system call on a first data storage system to create, remove, or modify an RDF group between the first data storage system and an... | 07/03/2007 |
| 7237086 | Configuring a management module through a graphical user interface for use in a computer system A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the customization program to customize the baseboard management controller based ... | 06/26/2007 |
| 7237087 | Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configura... | 06/26/2007 |
| 7233167 | Block symmetrization in a field programmable gate array An FPGA architecture has top, middle and low levels. The top level is an array of B16×16 tiles enclosed by I/O blocks. The routing resources in the middle level are expressway routing channels including interconnect conductors. At the lowest level, there are block ... | 06/19/2007 |
