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| Number | Title | Issue Date |
| 8015390 | Dissimilar processor synchronization in fly-by-wire high integrity computing platforms and displays A flight control system includes an output device, a first processor, and a second processor. The second processor is dissimilar to the first processor. The flight control system also includes a first arbitration device coupled to the first processor and a second ar... | 09/06/2011 |
| 7970735 | Cross varying dimension support for analysis services engine A data processing and analysis system is provided. The system includes an analysis engine that queries one or more components of data. A rules component specifies a relationship between at least one dimension of the data with respect to at least one other dimension ... | 06/28/2011 |
| 7441098 | Conditional execution of instructions in a computer A method of executing instructions in a computer system on operands containing a plurality of packed objects in respective lanes of the operand is described. Each instruction defines an operation and contains a condition setting indicator settable independently of t... | 10/21/2008 |
| 7373490 | Emptying packed data state during execution of packed data instructions A method in a computer system, one embodiment includes accessing a packed data instruction and generating a corresponding set of control bits to cause a processor to alter a top of stack to zero of a programmer visible register file, accessing a floating point instr... | 05/13/2008 |
| 7337190 | Apparatus and method for hardware-based file system A hardware-based file system includes multiple linked sub-modules that perform functions ancillary to client data handling. Each sub-module is associated with a metadata cache. A doubly-rooted structure is used to store each file system object at successive checkpoi... | 02/26/2008 |
| 7325082 | System and method for guaranteeing transactional fairness among multiple requesters A system and method for guaranteeing transactional fairness among multiple requesters contending for a common resource in a cache-coherent multiprocessor system is described. Batch processing is used to control servicing of multiple requests made by multiple request... | 01/29/2008 |
| 7318218 | System and method for processor thread for software debugging A system and method for using a processor thread as a debugger is presented. A computer system boots up and initiates a debugger thread. The debugger thread loads a robust, debugger operating system and executes the debugger operating system. Once the debugger threa... | 01/08/2008 |
| 7315517 | Non-blocking WDM optical networks A system is disclosed for implementing WDM optical networks, without blocking, and without the need for wavelength converters. The method is based on a hypercube topology for connecting the nodes, and a novel algorithm for constructing a routing tree such that block... | 01/01/2008 |
| 7268788 | Associative processing for three-dimensional graphics Associative processing methods and apparatus are described for processing graphics data for three-dimensional graphic displays, e.g., in three-dimensional games. A texture, which comprises a bitmap image used to apply a design onto the surface of a 3D computer model... | 09/11/2007 |
| 7266151 | Method and system for performing motion estimation using logarithmic search A method, apparatus,and system for performing motion estimation using a logarithmic search are described. One or more image signal processing engines including a plurality of processing elements are employed. The one or more image signal processing engines are mutua... | 09/04/2007 |
| 7191310 | Parallel processor and image processing apparatus adapted for nonlinear processing through selection via processor element numbers A parallel processor includes a global processor which interprets a program and controls the entirety of the parallel processor. A processor-element block includes a plurality of processor elements each comprising a register file and an operation array for processin... | 03/13/2007 |
| 7185226 | Fault tolerance in a supercomputer through dynamic repartitioning A multiprocessor, parallel computer is made tolerant to hardware failures by providing extra groups of redundant standby processors and by designing the system so that these extra groups of processors can be swapped with any group which experiences a hardware failur... | 02/27/2007 |
| 7146529 | System and method for processor thread acting as a system service processor A system and method for a processor thread acting as a system service provider is presented. A computer system boots up and initiates a service thread. The service thread is responsible for service related tasks, such as ECC checks and hardware log error checks. The... | 12/05/2006 |
| 7127528 | Caching process data of a slow network in a fast network environment A caching method and system for a control system having a fast network and a slow network that each contain devices involved in the control of a process is disclosed. The cache is disposed in a gateway interface device interconnected with both the fast and the slow ... | 10/24/2006 |
| 7103639 | Method and apparatus for processing unit synchronization for scalable parallel processing The present invention flexibly manages the formation of a partition from a plurality of independently executing cells (discrete hardware entities comprising system resources) in preparation for the instantiation of an operating system instance upon the partition. Sp... | 09/05/2006 |
| 7103764 | Parallel port with direct memory access capabilities The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller th... | 09/05/2006 |
| 7073048 | Cascaded microcomputer array and method A microcomputer array and method having a hyper-scalable, real-time monitoring and debug architecture in which several microcomputers are cascaded together into a single, more powerful unit. A cascaded instruction pipeline and related control circuitry allow a plura... | 07/04/2006 |
| 7051150 | Scalable on chip network A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum da... | 05/23/2006 |
| 7043562 | Irregular network Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on each backpla... | 05/09/2006 |
| 7042516 | Video signal switching apparatus and control method thereof The present invention is directed to a video signal switching apparatus having editing function to select an arbitrary video signal from plural video signals or carry out synthesis thereof, which allows an operation unit to be of modular configuration every respecti... | 05/09/2006 |
| 7035936 | Method for establishing a communication network based on topographic network devices and for transmitting a message through same A network for communicating a message is established by providing a network that includes topographic network devices and communication links interconnecting the topographic network devices. The topographic network devices each have a physical location represented b... | 04/25/2006 |
| 7030486 | High density integrated circuit package architecture This invention relates to a high density architecture for an integrated circuit package (10) in which a plurality of circuit communication wafers (12) are disposed in a stack with a plurality of cooling plates (14) between them, and wherein circ... | 04/18/2006 |
| 6973559 | Scalable hypercube multiprocessor network for massive parallel processing A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communicat... | 12/06/2005 |
| 6934283 | System and method for source defined packet routing A data communication system and method are provided to communicate in a multiprocessor interconnection network or other network. In one embodiment, the present system includes a number of logical circuits that are located in a number of nodes interconnected in a mul... | 08/23/2005 |
| 6934951 | Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing... | 08/23/2005 |
| 6918063 | System and method for fault tolerance in multi-node system A method and system for promoting fault tolerance in a multi-node computing system that provides deadlock-free message routing in the presence of node and/or link faults using only two rounds and, thus, requiring only two virtual channels to ensure deadlock freedom.... | 07/12/2005 |
| 6912608 | Methods and apparatus for pipelined bus Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a ... | 06/28/2005 |
| 6912626 | Method and apparatus for connecting a massively parallel processor array to a memory array in a bit serial manner A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circui... | 06/28/2005 |
| 6898657 | Autonomous signal processing resource for selective series processing of data in transit on communications paths in multi-processor arrangements A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal processing functions configurably embedded in series with the communicati... | 05/24/2005 |
| 6873287 | Signal processing arrangement The present invention relates to a method and an arrangement suitable for embedded signal processing, comprising a number of computational units (100), each computational unit comprising a number of processing elements (20) capable of working independe... | 03/29/2005 |
| 6769056 | Methods and apparatus for manifold array processing A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. ... | 07/27/2004 |
| 6754892 | Instruction packing for an advanced microprocessor A process for packing an instruction word including providing a word value representing an instruction word into which an operation is to be fit be equal to some initial value having a plurality of portions representing constraints, operating on the initial value of... | 06/22/2004 |
| 6754735 | Single descriptor scatter gather data transfer to or from a host processor A processing system includes a processing device and a host processor operatively coupled to the processing device via a system bus, and implements a scatter gather data transfer technique. The host processor is configurable to control the transfer of information to... | 06/22/2004 |
| 6741552 | Fault-tolerant, highly-scalable cell switching architecture Generally speaking, the cell switching architecture of the present invention offers a powerful, simple, and in many ways elegant solution to the problem of providing cost-effective, high-bandwidth, fault-tolerant cell switching. The architecture is based on a networ... | 05/25/2004 |
| 6680915 | Distributed computing system using virtual buses and data communication method for the same A router, which is basically a point-to-point communication router, is devised for the BUS-like communication between processors. Therefore, it is named as `Virtual Bus`. One processor is connected to one router and the router can be connected in one dime... | 01/20/2004 |
| 6609189 | Cycle segmented prefix circuits The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing implementations grow quadratically with the issue width and the... | 08/19/2003 |
| 6598145 | Irregular network Irregularities are provided in at least one dimension of a torus or mesh network for lower average path length and lower maximum channel load while increasing tolerance for omitted end-around connections. In preferred embodiments, all nodes supported on e... | 07/22/2003 |
| 6526375 | Self-configuring store-and-forward computer network In a self-configuring store-and-forward computer network, a plurality of processors are each housed in an enclosure having a top surface and a bottom surface. Each processor has an associated block identification number. An array of m by n radially symmet... | 02/25/2003 |
| 6510539 | System and method for physically modeling electronic modules wiring A computer program receives a large plurality of module design parameters and provides as output a graphical representation of the design together with text files that rate module wireability, including die pad position, attachment of each die pad to its ... | 01/21/2003 |
| 6487456 | Method and apparatus for creating a selectable electrical characteristic A device having a variable output electrical characteristic includes first and second output terminals and a number of switching circuits, each switching circuit having two states. One of the states produces a first electrical effect (such as an increased... | 11/26/2002 |
